E2900 problems
Hello not too experienced with E2900, we have a problem, it will not boot
Any help or advice how to progress would be appreciated also any indication as to what the problem may be.
SB2 and SB4 have been disabled manually.
Thanks in advance
Console output LOM
lom>
lom>poweron
/N0/PS0: powered on
Fri Jul 20 07:29:48 noname.example.com lom: SysEvent 5 /N0/PS0, power state, On (5,1)
/N0/PS1: powered on
Fri Jul 20 07:29:49 noname.example.com lom: SysEvent 5 /N0/PS1, power state, On (5,1)
/N0/PS2: powered on
Fri Jul 20 07:29:50 noname.example.com lom: SysEvent 5 /N0/PS2, power state, On (5,1)
/N0/PS3: powered on
Fri Jul 20 07:29:51 noname.example.com lom: SysEvent 5 /N0/PS3, power state, On (5,1)
/N0/FT0: powered on
Powering boards on ...
Fri Jul 20 07:30:06 noname.example.com lom: /N0/FT0, fan speed, Low (4,1)
Fri Jul 20 07:31:55 noname.example.com lom: Agent {/N0/SB2/P0/C0} is disabled.
Fri Jul 20 07:31:55 noname.example.com lom: Agent {/N0/SB2/P0/C1} is disabled.
Fri Jul 20 07:31:55 noname.example.com lom: Port {/N0/SB2/P0} is disabled.
Fri Jul 20 07:31:56 noname.example.com lom: Agent {/N0/SB2/P1/C0} is disabled.
Fri Jul 20 07:31:56 noname.example.com lom: Agent {/N0/SB2/P1/C1} is disabled.
Fri Jul 20 07:31:56 noname.example.com lom: Port {/N0/SB2/P1} is disabled.
Fri Jul 20 07:32:01 noname.example.com lom: Agent {/N0/SB2/P2/C0} is disabled.
Fri Jul 20 07:32:01 noname.example.com lom: Agent {/N0/SB2/P2/C1} is disabled.
Fri Jul 20 07:32:01 noname.example.com lom: Port {/N0/SB2/P2} is disabled.
Fri Jul 20 07:32:02 noname.example.com lom: Agent {/N0/SB2/P3/C0} is disabled.
Fri Jul 20 07:32:02 noname.example.com lom: Agent {/N0/SB2/P3/C1} is disabled.
Fri Jul 20 07:32:02 noname.example.com lom: Port {/N0/SB2/P3} is disabled.
Fri Jul 20 07:32:06 noname.example.com lom: Excluded unusable, unlicensed, failed or disabled board: /N0/SB2
Fri Jul 20 07:33:00 noname.example.com lom: Agent {/N0/SB4/P0/C0} is disabled.
Fri Jul 20 07:33:00 noname.example.com lom: Agent {/N0/SB4/P0/C1} is disabled.
Fri Jul 20 07:33:01 noname.example.com lom: Port {/N0/SB4/P0} is disabled.
Fri Jul 20 07:33:01 noname.example.com lom: Agent {/N0/SB4/P1/C0} is disabled.
Fri Jul 20 07:33:01 noname.example.com lom: Agent {/N0/SB4/P1/C1} is disabled.
Fri Jul 20 07:33:01 noname.example.com lom: Port {/N0/SB4/P1} is disabled.
Fri Jul 20 07:33:07 noname.example.com lom: Agent {/N0/SB4/P2/C0} is disabled.
Fri Jul 20 07:33:07 noname.example.com lom: Agent {/N0/SB4/P2/C1} is disabled.
Fri Jul 20 07:33:07 noname.example.com lom: Port {/N0/SB4/P2} is disabled.
Fri Jul 20 07:33:07 noname.example.com lom: Agent {/N0/SB4/P3/C0} is disabled.
Fri Jul 20 07:33:07 noname.example.com lom: Agent {/N0/SB4/P3/C1} is disabled.
Fri Jul 20 07:33:07 noname.example.com lom: Port {/N0/SB4/P3} is disabled.
Fri Jul 20 07:33:11 noname.example.com lom: Excluded unusable, unlicensed, failed or disabled board: /N0/SB4
Testing CPU Boards ...
{/N0/SB0/P2/C0} Running CPU POR and Set Clocks
{/N0/SB0/P0/C0} Running CPU POR and Set Clocks
{/N0/SB0/P3/C0} Running CPU POR and Set Clocks
{/N0/SB0/P1/C0} Running CPU POR and Set Clocks
{/N0/SB0/P2/C0} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P0/C0} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P3/C0} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P1/C0} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P2/C0} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P3/C0} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P0/C0} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P1/C0} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2/C0} Use is subject to license terms.
{/N0/SB0/P0/C0} Use is subject to license terms.
{/N0/SB0/P3/C0} Use is subject to license terms.
{/N0/SB0/P1/C0} Use is subject to license terms.
{/N0/SB0/P2/C0} Running Basic CPU
{/N0/SB0/P3/C0} Running Basic CPU
{/N0/SB0/P2/C1} Running Basic CPU
{/N0/SB0/P0/C0} Running Basic CPU
{/N0/SB0/P3/C1} Running Basic CPU
{/N0/SB0/P1/C0} Running Basic CPU
{/N0/SB0/P2/C0} Subtest: Setting Fireplane Config Registers for aid 0x2
{/N0/SB0/P0/C1} Running Basic CPU
{/N0/SB0/P1/C1} Running Basic CPU
{/N0/SB0/P0/C0} Subtest: Setting Fireplane Config Registers
{/N0/SB0/P1/C0} Subtest: Setting Fireplane Config Registers for aid 0x1
{/N0/SB0/P3/C0} Subtest: Setting Fireplane Config Registers for aid 0x3
{/N0/SB0/P2/C1} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P0/C1} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P1/C1} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P3/C1} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P0/C0} Subtest: Display CPU Version, frequency
{/N0/SB0/P1/C0} Subtest: Display CPU Version, frequency
{/N0/SB0/P0/C1} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P1/C1} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2/C0} Subtest: Display CPU Version, frequency
{/N0/SB0/P3/C0} Subtest: Display CPU Version, frequency
{/N0/SB0/P0/C0} Version register = 003e0019.22000507
{/N0/SB0/P2/C1} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P1/C0} Version register = 003e0019.22000507
{/N0/SB0/P3/C1} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P0/C1} Use is subject to license terms.
{/N0/SB0/P2/C0} Version register = 003e0019.22000507
{/N0/SB0/P3/C0} Version register = 003e0019.22000507
{/N0/SB0/P1/C1} Use is subject to license terms.
{/N0/SB0/P2/C1} Use is subject to license terms.
{/N0/SB0/P3/C1} Use is subject to license terms.
{/N0/SB0/P0/C0} CPU features = 1c5d738f.687208ff
{/N0/SB0/P2/C0} CPU features = 1c5d738f.687208ff
{/N0/SB0/P1/C0} CPU features = 1c5d738f.687208ff
{/N0/SB0/P3/C0} CPU features = 1c5d738f.687208ff
{/N0/SB0/P0/C1} Subtest: I-Cache Initialization
{/N0/SB0/P2/C1} Subtest: I-Cache Initialization
{/N0/SB0/P1/C1} Subtest: I-Cache Initialization
{/N0/SB0/P3/C1} Subtest: I-Cache Initialization
{/N0/SB0/P0/C0} Ecache Control Register 0007e640.bc2b0800
{/N0/SB0/P1/C0} Ecache Control Register 0007e640.bc2b0800
{/N0/SB0/P0/C1} Subtest: D-Cache Initialization
{/N0/SB0/P1/C1} Subtest: D-Cache Initialization
{/N0/SB0/P2/C0} Ecache Control Register 0007e640.bc2b0800
{/N0/SB0/P3/C0} Ecache Control Register 0007e640.bc2b0800
{/N0/SB0/P2/C1} Subtest: D-Cache Initialization
{/N0/SB0/P0/C0} Cpu/System ratio = 12, cpu actual frequency = 1800
{/N0/SB0/P3/C1} Subtest: D-Cache Initialization
{/N0/SB0/P1/C0} Cpu/System ratio = 12, cpu actual frequency = 1800
{/N0/SB0/P0/C1} Subtest: W-Cache Initialization
{/N0/SB0/P1/C1} Subtest: W-Cache Initialization
{/N0/SB0/P2/C0} Cpu/System ratio = 12, cpu actual frequency = 1800
{/N0/SB0/P3/C0} Cpu/System ratio = 12, cpu actual frequency = 1800
{/N0/SB0/P2/C1} Subtest: W-Cache Initialization
{/N0/SB0/P3/C1} Subtest: W-Cache Initialization
{/N0/SB0/P0/C0} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P1/C0} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P0/C1} Subtest: P-Cache Initialization
{/N0/SB0/P1/C1} Subtest: P-Cache Initialization
{/N0/SB0/P2/C0} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P3/C0} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P2/C1} Subtest: P-Cache Initialization
{/N0/SB0/P3/C1} Subtest: P-Cache Initialization
{/N0/SB0/P2/C0} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P3/C0} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2/C1} Subtest: Branch Prediction Initialization
{/N0/SB0/P3/C1} Subtest: Branch Prediction Initialization
{/N0/SB0/P2/C0} Running Test Large Tag Arrays and Enable MMU
{/N0/SB0/P0/C0} Running Test Large Tag Arrays and Enable MMU
{/N0/SB0/P3/C0} Running Test Large Tag Arrays and Enable MMU
{/N0/SB0/P1/C0} Running Test Large Tag Arrays and Enable MMU
{/N0/SB0/P2/C1} Running Test Large Tag Arrays and Enable MMU
{/N0/SB0/P0/C1} Running Test Large Tag Arrays and Enable MMU
{/N0/SB0/P3/C1} Running Test Large Tag Arrays and Enable MMU
{/N0/SB0/P1/C1} Running Test Large Tag Arrays and Enable MMU
{/N0/SB0/P2/C0} Use is subject to license terms.
{/N0/SB0/P0/C0} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P3/C0} Use is subject to license terms.
{/N0/SB0/P1/C0} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2/C1} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P0/C1} Subtest: Branch Prediction Initialization
{/N0/SB0/P3/C1} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P1/C1} Subtest: Branch Prediction Initialization
{/N0/SB0/P2/C0} Subtest: I-Cache Initialization
{/N0/SB0/P0/C0} Use is subject to license terms.
{/N0/SB0/P3/C0} Subtest: I-Cache Initialization
{/N0/SB0/P1/C0} Use is subject to license terms.
{/N0/SB0/P2/C1} Subtest: Fast Init. Verification Test
{/N0/SB0/P0/C1} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P3/C1} Subtest: Fast Init. Verification Test
{/N0/SB0/P1/C1} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P2/C0} Subtest: D-Cache Initialization
{/N0/SB0/P0/C0} Subtest: I-Cache Initialization
{/N0/SB0/P3/C0} Subtest: D-Cache Initialization
{/N0/SB0/P1/C0} Subtest: I-Cache Initialization
{/N0/SB0/P2/C1} Subtest: IMMU Initialization
{/N0/SB0/P0/C1} Subtest: Fast Init. Verification Test
{/N0/SB0/P1/C1} Subtest: Fast Init. Verification Test
{/N0/SB0/P3/C1} Subtest: IMMU Initialization
{/N0/SB0/P0/C0} Subtest: D-Cache Initialization
{/N0/SB0/P1/C0} Subtest: D-Cache Initialization
{/N0/SB0/P2/C0} Subtest: W-Cache Initialization
{/N0/SB0/P0/C1} Subtest: IMMU Initialization
{/N0/SB0/P3/C0} Subtest: W-Cache Initialization
{/N0/SB0/P1/C1} Subtest: IMMU Initialization
{/N0/SB0/P2/C1} Subtest: DMMU Initialization
{/N0/SB0/P3/C1} Subtest: DMMU Initialization
{/N0/SB0/P0/C0} Subtest: W-Cache Initialization
{/N0/SB0/P1/C0} Subtest: W-Cache Initialization
{/N0/SB0/P0/C1} Subtest: DMMU Initialization
{/N0/SB0/P1/C1} Subtest: DMMU Initialization
{/N0/SB0/P2/C0} Subtest: P-Cache Initialization
{/N0/SB0/P3/C0} Subtest: P-Cache Initialization
{/N0/SB0/P2/C1} Subtest: Map LPOST to local space
{/N0/SB0/P3/C1} Subtest: Map LPOST to local space
{/N0/SB0/P0/C0} Subtest: P-Cache Initialization
{/N0/SB0/P1/C0} Subtest: P-Cache Initialization
{/N0/SB0/P0/C1} Subtest: Map LPOST to local space
{/N0/SB0/P2/C0} Subtest: Branch Prediction Initialization
{/N0/SB0/P3/C0} Subtest: Branch Prediction Initialization
{/N0/SB0/P1/C1} Subtest: Map LPOST to local space
{/N0/SB0/P2/C1} Subtest: L2-Cache Initialization of first 1K
{/N0/SB0/P3/C1} Subtest: L2-Cache Initialization of first 1K
{/N0/SB0/P0/C0} Subtest: Branch Prediction Initialization
{/N0/SB0/P2/C0} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P3/C0} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P1/C0} Subtest: Branch Prediction Initialization
{/N0/SB0/P0/C1} Subtest: L2-Cache Initialization of first 1K
{/N0/SB0/P1/C1} Subtest: L2-Cache Initialization of first 1K
{/N0/SB0/P2/C0} Subtest: Fast Init. Verification Test
{/N0/SB0/P3/C0} Subtest: Fast Init. Verification Test
{/N0/SB0/P2/C1} Subtest: L2-Cache Initialization
{/N0/SB0/P3/C1} Subtest: L2-Cache Initialization
{/N0/SB0/P0/C0} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P1/C0} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P2/C0} Subtest: IMMU Initialization
{/N0/SB0/P3/C0} Subtest: IMMU Initialization
{/N0/SB0/P0/C1} Subtest: L2-Cache Initialization
{/N0/SB0/P1/C1} Subtest: L2-Cache Initialization
{/N0/SB0/P0/C0} Subtest: Fast Init. Verification Test
{/N0/SB0/P1/C0} Subtest: Fast Init. Verification Test
{/N0/SB0/P0/C0} Running FPU Tests
{/N0/SB0/P2/C0} Running FPU Tests
{/N0/SB0/P1/C0} Running FPU Tests
{/N0/SB0/P3/C0} Running FPU Tests
{/N0/SB0/P0/C1} Running FPU Tests
{/N0/SB0/P1/C1} Running FPU Tests
{/N0/SB0/P0/C0} Subtest: IMMU Initialization
{/N0/SB0/P2/C1} Running FPU Tests
{/N0/SB0/P3/C1} Running FPU Tests
{/N0/SB0/P1/C0} Subtest: IMMU Initialization
{/N0/SB0/P0/C0} Subtest: DMMU Initialization
{/N0/SB0/P1/C0} Subtest: DMMU Initialization
{/N0/SB0/P2/C0} Subtest: DMMU Initialization
{/N0/SB0/P3/C0} Subtest: DMMU Initialization
{/N0/SB0/P2/C0} Subtest: Map LPOST to local space
{/N0/SB0/P3/C0} Subtest: Map LPOST to local space
{/N0/SB0/P0/C0} Subtest: Map LPOST to local space
{/N0/SB0/P1/C0} Subtest: Map LPOST to local space
{/N0/SB0/P2/C0} Subtest: L2-Cache Initialization of first 1K
{/N0/SB0/P3/C0} Subtest: L2-Cache Initialization of first 1K
{/N0/SB0/P2/C0} Running Basic Ecache
{/N0/SB0/P0/C0} Running Basic Ecache
{/N0/SB0/P3/C0} Running Basic Ecache
{/N0/SB0/P1/C0} Running Basic Ecache
{/N0/SB0/P0/C0} Subtest: L2-Cache Initialization of first 1K
{/N0/SB0/P2/C0} Subtest: L2-Cache Initialization
{/N0/SB0/P3/C0} Subtest: L2-Cache Initialization
{/N0/SB0/P1/C0} Subtest: L2-Cache Initialization of first 1K
{/N0/SB0/P0/C0} Subtest: L2-Cache Initialization
{/N0/SB0/P1/C0} Subtest: L2-Cache Initialization
{/N0/SB0/P2/C0} Subtest: L3-Cache Initialization of first 1K
{/N0/SB0/P3/C0} Subtest: L3-Cache Initialization of first 1K
{/N0/SB0/P0/C0} Subtest: L3-Cache Initialization of first 1K
{/N0/SB0/P1/C0} Subtest: L3-Cache Initialization of first 1K
{/N0/SB0/P2/C0} Subtest: L3-Cache Initialization
{/N0/SB0/P0/C0} Subtest: L3-Cache Initialization
{/N0/SB0/P3/C0} Subtest: L3-Cache Initialization
{/N0/SB0/P1/C0} Subtest: L3-Cache Initialization
{/N0/SB0/P2/C0} Running Memory Registers Tests
{/N0/SB0/P0/C0} Running Memory Registers Tests
{/N0/SB0/P3/C0} Running Memory Registers Tests
{/N0/SB0/P1/C0} Running Memory Registers Tests
{/N0/SB0/P2/C0} Subtest: Disable Memory Controllers
{/N0/SB0/P0/C0} Subtest: Disable Memory Controllers
{/N0/SB0/P3/C0} Subtest: Disable Memory Controllers
{/N0/SB0/P1/C0} Subtest: Disable Memory Controllers
{/N0/SB0/P0/C0} Running Memory Configuration Tests
{/N0/SB0/P2/C0} Running Memory Configuration Tests
{/N0/SB0/P1/C0} Running Memory Configuration Tests
{/N0/SB0/P3/C0} Running Memory Configuration Tests
{/N0/SB0/P0/C0} Subtest: Memory Controller Configuration
{/N0/SB0/P1/C0} Subtest: Memory Controller Configuration
{/N0/SB0/P2/C0} Subtest: Memory Controller Configuration
{/N0/SB0/P3/C0} Subtest: Memory Controller Configuration
{/N0/SB0/P2/C0} set_panther_rd_bypass_wr: cpuno 2 ctl_addr 00000000.00000030 val 37064778.0c060301
{/N0/SB0/P3/C0} set_panther_rd_bypass_wr: cpuno 3 ctl_addr 00000000.00000030 val 37064778.0c060301
{/N0/SB0/P0/C0} set_panther_rd_bypass_wr: cpuno 0 ctl_addr 00000000.00000030 val 37064778.0c060301
{/N0/SB0/P1/C0} set_panther_rd_bypass_wr: cpuno 1 ctl_addr 00000000.00000030 val 37064778.0c060301
{/N0/SB0/P0/C0} Subtest: Memory DIMMs Init
{/N0/SB0/P1/C0} Subtest: Memory DIMMs Init
{/N0/SB0/P2/C0} Subtest: Memory DIMMs Init
{/N0/SB0/P3/C0} Subtest: Memory DIMMs Init
{/N0/SB0/P0/C0} Subtest: UP Memory Clear
{/N0/SB0/P1/C0} Subtest: UP Memory Clear
{/N0/SB0/P2/C0} Subtest: UP Memory Clear
{/N0/SB0/P3/C0} Subtest: UP Memory Clear
{/N0/SB0/P0/C0} Running Memory Tests
{/N0/SB0/P1/C0} Running Memory Tests
{/N0/SB0/P0/C1} Running Memory Tests
{/N0/SB0/P1/C1} Running Memory Tests
{/N0/SB0/P0/C0} Subtest: Enable Correctable Error Traps
{/N0/SB0/P1/C0} Subtest: Enable Correctable Error Traps
{/N0/SB0/P0/C1} Subtest: Enable Correctable Error Traps
{/N0/SB0/P2/C0} Running Memory Tests
{/N0/SB0/P1/C1} Subtest: Enable Correctable Error Traps
{/N0/SB0/P3/C0} Running Memory Tests
{/N0/SB0/P2/C1} Running Memory Tests
{/N0/SB0/P3/C1} Running Memory Tests
{/N0/SB0/P2/C0} Subtest: Enable Correctable Error Traps
{/N0/SB0/P3/C0} Subtest: Enable Correctable Error Traps
{/N0/SB0/P2/C1} Subtest: Enable Correctable Error Traps
{/N0/SB0/P3/C1} Subtest: Enable Correctable Error Traps
{/N0/SB0/P0/C0} Running Advanced CPU Tests
{/N0/SB0/P2/C0} Running Advanced CPU Tests
{/N0/SB0/P1/C0} Running Advanced CPU Tests
{/N0/SB0/P3/C0} Running Advanced CPU Tests
{/N0/SB0/P0/C1} Running Advanced CPU Tests
{/N0/SB0/P2/C1} Running Advanced CPU Tests
{/N0/SB0/P1/C1} Running Advanced CPU Tests
{/N0/SB0/P3/C1} Running Advanced CPU Tests
{/N0/SB0/P2/C0} Running CPU ECC Tests
{/N0/SB0/P0/C0} Running CPU ECC Tests
{/N0/SB0/P3/C0} Running CPU ECC Tests
{/N0/SB0/P1/C0} Running CPU ECC Tests
{/N0/SB0/P2/C1} Running CPU ECC Tests
{/N0/SB0/P0/C1} Running CPU ECC Tests
{/N0/SB0/P3/C1} Running CPU ECC Tests
{/N0/SB0/P1/C1} Running CPU ECC Tests
{/N0/SB0/P0/C0} Running System Level Tests
{/N0/SB0/P2/C0} Running System Level Tests
{/N0/SB0/P1/C0} Running System Level Tests
{/N0/SB0/P3/C0} Running System Level Tests
{/N0/SB0/P0/C1} Running System Level Tests
{/N0/SB0/P2/C1} Running System Level Tests
{/N0/SB0/P1/C1} Running System Level Tests
{/N0/SB0/P0/C0} Subtest: Invalidate Caches
{/N0/SB0/P1/C0} Subtest: Invalidate Caches
{/N0/SB0/P3/C1} Running System Level Tests
{/N0/SB0/P0/C1} Subtest: Invalidate Caches
{/N0/SB0/P2/C0} Subtest: Invalidate Caches
{/N0/SB0/P1/C1} Subtest: Invalidate Caches
{/N0/SB0/P3/C0} Subtest: Invalidate Caches
{/N0/SB0/P2/C1} Subtest: Invalidate Caches
{/N0/SB0/P3/C1} Subtest: Invalidate Caches
{/N0/SB0/P2/C0} Running Board Memory Interleave
{/N0/SB0/P3/C0} Running Board Memory Interleave
{/N0/SB0/P0/C0} Running Board Memory Interleave
{/N0/SB0/P1/C0} Running Board Memory Interleave
{/N0/SB0/P2/C0} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P3/C0} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P0/C0} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P1/C0} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P0/C0} Passed
{/N0/SB0/P1/C0} Passed
{/N0/SB0/P0/C1} Passed
{/N0/SB0/P1/C1} Passed
{/N0/SB0/P2/C0} Passed
{/N0/SB0/P3/C0} Passed
{/N0/SB0/P2/C1} Passed
{/N0/SB0/P3/C1} Passed
{/N0/SB0/P0} Passed
{/N0/SB0/P1} Passed
{/N0/SB0/P2} Passed
{/N0/SB0/P3} Passed
Testing IO Boards ...
Copying IO PROM to CPU DRAM
....................................................
{/N0/SB0/P0/C0} Running PCI IO Controller Basic Tests
{/N0/SB0/P0/C0} Jumping to memory 00000000.00000020 [00000010]
{/N0/SB0/P0/C0} System PCI IO post code running from memory
{/N0/SB0/P0/C0} @(#) lpost5.20.3 2006/10/21 06:37
{/N0/SB0/P0/C0} Running PCI IO Controller Functional Tests
{/N0/SB0/P0/C0} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P0/C0} Use is subject to license terms.
{/N0/SB0/P0/C0} Subtest: PCI IO Controller Register Initialization for aid 0x18
{/N0/SB0/P0/C0} Running PCI IO Controller Ecc Tests
{/N0/SB0/P0/C0} Running Bridge Tests
{/N0/SB0/P0/C0} Subtest: PCI Bridge Initialization for aid 0x18
{/N0/SB0/P0/C0} Running SBBC Basic Tests
{/N0/SB0/P0/C0} Subtest: SBBC PCI Reg Initialization for aid 0x18
{/N0/SB0/P0/C0} Running Ethernet0 Tests
{/N0/SB0/P0/C0} Subtest: Ethernet0 PCI Config Space Test for aid 0x18
{/N0/SB0/P0/C0} Running Ethernet1 Tests
{/N0/SB0/P0/C0} Subtest: Ethernet1 PCI Config Space Test for aid 0x18
{/N0/SB0/P0/C0} Running IDE Controller Tests
{/N0/SB0/P0/C0} Subtest: IDE Controller PCI Config Space Test for aid 0x18
{/N0/SB0/P0/C0} Running SCSI Controller Tests
{/N0/SB0/P0/C0} Subtest: SCSI Controller PCI Config Space Test for aid 0x18
{/N0/SB0/P0/C0} Running Probe io Devices
{/N0/SB0/P0/C0} Running PCI IO Controller Basic Tests
{/N0/SB0/P0/C0} Subtest: PCI IO Controller Register Initialization for aid 0x19
{/N0/SB0/P0/C0} Running PCI IO Controller Functional Tests
{/N0/SB0/P0/C0} Running PCI IO Controller Ecc Tests
{/N0/SB0/P0/C0} Running Ethernet0 Tests
{/N0/SB0/P0/C0} Subtest: Ethernet0 PCI Config Space Test for aid 0x19
{/N0/SB0/P0/C0} Running Ethernet1 Tests
{/N0/SB0/P0/C0} Subtest: Ethernet1 PCI Config Space Test for aid 0x19
{/N0/SB0/P0/C0} Running Probe io Devices
{/N0/SB0/P0/C0} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P0/C0} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P0/C0} Use is subject to license terms.
{/N0/SB0/P0/C1} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P0/C1} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P0/C1} Use is subject to license terms.
{/N0/IB6/P0} Passed
{/N0/IB6/P1} Passed
Testing domain ...
{/N0/SB0/P0/C0} Running Domain Level Tests
{/N0/SB0/P0/C0} Subtest: Mapping IO SRAM
{/N0/SB0/P0/C0} Subtest: Memory interleaving config
{/N0/SB0/P0/C0} Running Domain Basic Tests
{/N0/SB0/P0/C0} Subtest: Cross Call Test
{/N0/SB0/P0/C0} Running Domain Advanced Tests
{/N0/SB0/P0/C0} Subtest: MP Memory Clear Test
{/N0/SB0/P0/C0} CORE 1 clearing 00000000.00000000 to 00000001.00000000
{/N0/SB0/P0/C0} CORE 2 clearing 00000001.00000000 to 00000002.00000000
{/N0/SB0/P0/C0} CORE 3 clearing 00000002.00000000 to 00000003.00000000
{/N0/SB0/P0/C0} CORE 0 clearing 00000003.00000000 to 00000004.00000000
{/N0/SB0/P0/C0} Running Domain Stick Sync Tests
{/N0/SB0/P0/C0} Subtest: Sync. Stick Registers Test
{/N0/SB0/P0/C0} Running Domain Verify Stick Sync Tests
{/N0/SB0/P0/C0} Subtest: Verify Sync. Stick Registers Test
{/N0/SB0/P0/C0} DCB_DECOMP_OBP command succeeded
{/N0/SB0/P0/C0} Decompress OBP done
{/N0/SB0/P0/C0} DCB_ENTER_OBP command succeeded
{/N0/SB0/P1/C0} DCB_ENTER_OBP command succeeded
{/N0/SB0/P0/C1} DCB_ENTER_OBP command succeeded
{/N0/SB0/P1/C1} DCB_ENTER_OBP command succeeded
{/N0/SB0/P2/C0} DCB_ENTER_OBP command succeeded
{/N0/SB0/P3/C0} DCB_ENTER_OBP command succeeded
{/N0/SB0/P2/C1} DCB_ENTER_OBP command succeeded
{/N0/SB0/P3/C1} DCB_ENTER_OBP command succeeded
Entering OBP ...
Authorized users only. All activity may be monitored and reported.
Copyright 2006 Sun Microsystems, Inc. All rights reserved.
Use is subject to license terms.
SmartFirmware, Copyright (C) 1996-2001. All rights reserved.
{0} ok boot
SunOS Release 5.10 Version Generic_118833-33 64-bit
Copyright 1983-2006 Sun Microsystems, Inc. All rights reserved.
Use is subject to license terms.
Hardware watchdog enabled
Fri Jul 20 07:39:00 noname.example.com lom: Domain is not responding to interrupts.
Fri Jul 20 07:39:01 noname.example.com lom: Using default hang-policy (RESET).
Fri Jul 20 07:39:01 noname.example.com lom: Saving reset state data before XIR.
Fri Jul 20 07:39:01 noname.example.com lom: Resetting (XIR) domain.
Fri Jul 20 07:39:01 noname.example.com lom: Saving reset state data after XIR.
Fri Jul 20 07:39:01 noname.example.com lom: {/N0/SB0/P0/C0}
NOTICE: XIR on CPU 2
Fri Jul 20 07:39:03 noname.example.com lom:Regular AlternateMMU Interrupt
Fri Jul 20 07:39:03 noname.example.com lom: %g1: 00000000f05d5000 <unavailable>ffffffffffff0001 000000000000060c
Fri Jul 20 07:39:03 noname.example.com lom: %g2: 0000000000000001 <unavailable>ffffffffffffe000 000000000000000b
TL = 1, TT = 68. ERROR: Fast Data Access MMU Miss
TSTATE= 0x1407 [ccr = 0x0, asi = 0x0, pstate = 0x14, cwp = 0x7]
TPC= unix:reestablish_curthread+0x20 (00000000011768b8)
TNPC= genunix:const_seg_900000101+0x9fc (00000000011768bc)
SFSR= 000000000080800b, TAGACCESS = 00000300002d8000
D-SFAR = 00000300002d9781
TICK= 800000012de52aff, TICKCMP = ffffffffffffffff
TL = 1, TT = 34. ERROR: Alignment Error
TSTATE= 0x9900001403 [ccr = 0x99, asi = 0x0, pstate = 0x14, cwp = 0x3]
Fri Jul 20 07:39:04 noname.example.com lom: %g3: 0000000000000010 0000000000000020 0000000000000001 0000000000000003
Fri Jul 20 07:39:04 noname.example.com lom: %g4: 0000000000000000 000000000300cf68 0000000000000019 000000000180c000
Fri Jul 20 07:39:04 noname.example.com lom: %g5: 0000000001884c00 0000000000000034 00000000000000ff 000000007001c300
TNPC= 00000000f003a678
TICK= 800000012df23710, TICKCMP = ffffffffffffffff
TL = 1, TT = 34. ERROR: Alignment Error
TSTATE= 0x9900001403 [ccr = 0x99, asi = 0x0, pstate = 0x14, cwp = 0x3]
TPC= 00000000f003a674
TNPC= 00000000f003a678
TICK= 800000012e03a3f8, TICKCMP = ffffffffffffffff
TL = 1, TT = 34. ERROR: Alignment Error
TSTATE= 0x9900001403 [ccr = 0x99, asi = 0x0, pstate = 0x14, cwp = 0x3]
TPC= 00000000f003a674
TNPC= 00000000f003a678
TICK= 800000012e158d48, TICKCMP = ffffffffffffffff
Fri Jul 20 07:39:04 noname.example.com lom: %g6: 0000000000000010 0000000000000000 000000000180e500 0000000000018300
TL = 1, TT = 34. ERROR: Alignment Error
TSTATE= 0x9900001403 [ccr = 0x99, asi = 0x0, pstate = 0x14, cwp = 0x3]
TPC= 00000000f003a674
TNPC= 00000000f003a678
TICK= 800000012e273e58, TICKCMP = ffffffffffffffff
TL = 1, TT = 34. ERROR: Alignment Error
TSTATE= 0x9900001403 [ccr = 0x99, asi = 0x0, pstate = 0x14, cwp = 0x3]
TPC= 00000000f003a674
TNPC= 00000000f003a678
TICK= 800000012e392bf8, TICKCMP = ffffffffffffffff
TL = 1, TT = 34. ERROR: Alignment Error
TSTATE= 0x9900001403 [ccr = 0x99,Fri Jul 20 07:39:04 noname.example.com lom: %g7: 000000000180e000 0000000000000002 0000000000000000 0000000000000020
asi = 0x0, pstate = 0x14, cwp = 0x3]
TPC= 00000000f003a674
TNPC= 00000000f003a678
TICK= 800000012e4b22f8, TICKCMP = ffffffffffffffff
TL = 1, TT = 34. ERROR: Alignment Error
TSTATE= 0x9900001403 [ccr = 0x99, asi = 0x0, pstate = 0x14, cwp = 0x3]
TPC= 00000000f003a674
TNPC= 00000000f003a678
TICK= 800000012e5d1758, TICKCMP = ffffffffffffffff
ERROR: Error Trap Threshold Reached, Generating RED Mode Trap ...
Fri Jul 20 07:39:05 noname.example.com lom:
Fri Jul 20 07:39:05 noname.example.com lom: %pil: a
Fri Jul 20 07:39:05 noname.example.com lom:
Fri Jul 20 07:39:05 noname.example.com lom: %tick: 00000000002010e3 %tick_cmpr:8000000000000000
Fri Jul 20 07:39:05 noname.example.com lom: %sys_tick:000000008b8807d8 %sys_tick_cmpr: 0000000053761e90
Fri Jul 20 07:39:06 noname.example.com lom:
Fri Jul 20 07:39:06 noname.example.com lom: AFAR:0000000002c09c30 AFSR:0010000200000128
Fri Jul 20 07:39:06 noname.example.com lom: AFAR_2: 0000000002c09c30 AFSR_2: 0010000200000128
Fri Jul 20 07:39:06 noname.example.com lom:
Fri Jul 20 07:39:06 noname.example.com lom: Bank 0 MADR: 8001fe0000000000 Bank 1 MADR: 8001fe0000000400
Fri Jul 20 07:39:06 noname.example.com lom: Bank 2 MADR: 8001fe0000000800 Bank 3 MADR: 8001fe0000000c00
Fri Jul 20 07:39:06 noname.example.com lom:
Fri Jul 20 07:39:06 noname.example.com lom: %tl: 3
Fri Jul 20 07:39:06 noname.example.com lom: %tl %tpc %tnpc %tstate%tt
Fri Jul 20 07:39:07 noname.example.com lom: 3 00000000010078c0 00000000010078c4 0000001501003
Fri Jul 20 07:39:07 noname.example.com lom:%ccr: 00 %asi: 00 %cwp: 1 %pstate: 015 (AG PRIV PEF TSO)
Fri Jul 20 07:39:07 noname.example.com lom: 2 0000000001008ca8 0000000001008cac 4400041401034
{/N0/SB0/P0/C0} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P0/C0} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P0/C0} Use is subject to license terms.
Fri Jul 20 07:39:07 noname.example.com lom:%ccr: 44 %asi: 00 %cwp: 1 %pstate: 414 (MG PRIV PEF TSO)
{/N0/SB0/P1/C0} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P1/C0} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P1/C0} Use is subject to license terms.
{/N0/SB0/P0/C1} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P0/C1} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P0/C1} Use is subject to license terms.
{/N0/SB0/P1/C1} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P1/C1} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P1/C1} Use is subject to license terms.
{/N0/SB0/P2/C0} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P2/C0} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2/C0} Use is subject to license terms.
{/N0/SB0/P2/C0} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P2/C0} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2/C0} Use is subject to license terms.
{/N0/SB0/P2/C0} WARNING: Asynchronous Event.
Fri Jul 20 07:39:08 noname.example.com lom: 1 0000000001021c1c 0000000001021c20 0000001601068
{/N0/SB0/P2/C0} Component under test: /N0/SB0/P2 CPU
{/N0/SB0/P2/C0} Data Access Error from address 00000000.00000000. AFSR = 00000000.00000000
{/N0/SB0/P2/C0} Secondary AFAR 00000003.ffb8cb00, Secondary AFSR = 00000000.00000000
{/N0/SB0/P2/C0} AFSR1 EXT: 00000000.00000000 AFSR2 EXT: 00000000.00000000
{/N0/SB0/P2/C0} tl tt tstatetpctnpc
{/N0/SB0/P2/C0} 01 63 00000044.80000605 000007ff.f000c370 000007ff.f000c374
{/N0/SB0/P3/C0} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P3/C0} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P3/C0} Use is subject to license terms.
Fri Jul 20 07:39:09 noname.example.com lom:%ccr: 00 %asi: 00 %cwp: 1 %pstate: 016 (IE PRIV PEF TSO)
{/N0/SB0/P2/C1} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P2/C1} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
Fri Jul 20 07:39:09 noname.example.com lom:
{/N0/SB0/P2/C1} Use is subject to license terms.
{/N0/SB0/P3/C1} @(#) lpost5.20.3 2006/10/21 06:25
{/N0/SB0/P3/C1} Copyright 2006 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P3/C1} Use is subject to license terms.
Fri Jul 20 07:39:10 noname.example.com lom: %cansave: 6 %canrestore: 1 %otherwin: 0 %cleanwin: 1 %wstate: e
Fri Jul 20 07:39:10 noname.example.com lom:
Fri Jul 20 07:39:10 noname.example.com lom: ACTIVE WINDOWS
Fri Jul 20 07:39:10 noname.example.com lom: %cwp: 1
Fri Jul 20 07:39:10 noname.example.com lom: frame address (64-bit):fffffffffffffe80
Fri Jul 20 07:39:10 noname.example.com lom: PC of call instruction:0000000000000000
Fri Jul 20 07:39:10 noname.example.com lom: %o0-%o3: 0000000000000000 0000000000000000 0000000000000000 0000000000000005
Fri Jul 20 07:39:10 noname.example.com lom: %o4-%o7: 0000000000000000 0000000000000000 fffffffffffff681 0000000000000000
Fri Jul 20 07:39:10 noname.example.com lom: %l0-%l3: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
Fri Jul 20 07:39:10 noname.example.com lom: %l4-%l7: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
Fri Jul 20 07:39:10 noname.example.com lom: %i0-%i3: 0000000000000000 0000000001076eb0 0000000000000002 0000000000001000
Fri Jul 20 07:39:10 noname.example.com lom: %i4-%i7: 0000000000000000 0000000001076c00 fffffffffffff751 00000000010154fc
Fri Jul 20 07:39:10 noname.example.com lom:
Fri Jul 20 07:39:10 noname.example.com lom: %cwp: 0
Fri Jul 20 07:39:10 noname.example.com lom: frame address (64-bit):ffffffffffffff50
Fri Jul 20 07:39:10 noname.example.com lom: PC of call instruction:00000000010154fc
Fri Jul 20 07:39:10 noname.example.com lom: %o0-%o3: 0000000000000000 0000000001076eb0 0000000000000002 0000000000001000
Fri Jul 20 07:39:11 noname.example.com lom: %o4-%o7: 0000000000000000 0000000001076c00 fffffffffffff751 00000000010154fc
Fri Jul 20 07:39:11 noname.example.com lom: %l0-%l3: 000000000180c000 000000000180cb00 0000000000000000 0000000000000001
Fri Jul 20 07:39:12 noname.example.com lom: %l4-%l7: 000000000191d000 00000000f05cf020 0000000001014c00 0000000000000000
Fri Jul 20 07:39:12 noname.example.com lom: %i0-%i3: 000000004f530100 00000000f005a5d0 00000000deadbeef 00000000f05d39b0
Fri Jul 20 07:39:12 noname.example.com lom: %i4-%i7: 0000000000000000 0000000000005da8 0000000000000000 0000000000000000
Fri Jul 20 07:39:12 noname.example.com lom:
Fri Jul 20 07:39:12 noname.example.com lom:
Fri Jul 20 07:39:12 noname.example.com lom: UNUSED WINDOWS
Fri Jul 20 07:39:12 noname.example.com lom: %cwp: 7
Fri Jul 20 07:39:12 noname.example.com lom: frame address (32-bit):0000000000000000
Fri Jul 20 07:39:12 noname.example.com lom: PC of call instruction:0000000000000000
Fri Jul 20 07:39:12 noname.example.com lom: %o0-%o3: 000000004f530100 00000000f005a5d0 00000000deadbeef 00000000f05d39b0
Fri Jul 20 07:39:12 noname.example.com lom: %o4-%o7: 0000000000000000 0000000000005da8 0000000000000000 0000000000000000
Fri Jul 20 07:39:12 noname.example.com lom: %l0-%l3: 0000070003af9880 0000000000000000 000003000230cd50 0000000000000000
Fri Jul 20 07:39:12 noname.example.com lom: %l4-%l7: 000000000180b488 0000000087000000 0000000087000000 0000000001884c00
Fri Jul 20 07:39:12 noname.example.com lom: %i0-%i3: 0000000000000000 0000000000000000 000000004f530100 0000000000000000
Fri Jul 20 07:39:12 noname.example.com lom: %i4-%i7: 00000000f05d39b0 0000000000000000 00000000f05b7da1 00000000f0020844
Fri Jul 20 07:39:13 noname.example.com lom:
Fri Jul 20 07:39:14 noname.example.com lom: %cwp: 6
Fri Jul 20 07:39:14 noname.example.com lom: frame address (64-bit):00000000f05b85a0
Fri Jul 20 07:39:14 noname.example.com lom: PC of call instruction:00000000f0020844
Fri Jul 20 07:39:14 noname.example.com lom: %o0-%o3: 0000000000000000 0000000000000000 000000004f530100 0000000000000000
Fri Jul 20 07:39:14 noname.example.com lom: %o4-%o7: 00000000f05d39b0 0000000000000000 00000000f05b7da1 00000000f0020844
Fri Jul 20 07:39:14 noname.example.com lom: %l0-%l3: 0000000000000000 0000000000000003 00000000f05d35a8 0000000000000000
Fri Jul 20 07:39:14 noname.example.com lom: %l4-%l7: 0000000001833bf0 0000000000000000 0000000000000000 0000000080000000
Fri Jul 20 07:39:14 noname.example.com lom: %i0-%i3: 0000000000000000 0000000000000002 000000000180b898 00000000f05e10f8
Fri Jul 20 07:39:14 noname.example.com lom: %i4-%i7: 0000000000000000 00000000f05d39b0 00000000f05b7e51 00000000f000d3c4
Fri Jul 20 07:39:14 noname.example.com lom:
Fri Jul 20 07:39:14 noname.example.com lom: %cwp: 5
Fri Jul 20 07:39:14 noname.example.com lom: frame address (64-bit):00000000f05b8650
Fri Jul 20 07:39:14 noname.example.com lom: PC of call instruction:00000000f000d3c4
Fri Jul 20 07:39:14 noname.example.com lom: %o0-%o3: 0000000000000000 0000000000000002 000000000180b898 00000000f05e10f8
Fri Jul 20 07:39:14 noname.example.com lom: %o4-%o7: 0000000000000000 00000000f05d39b0 00000000f05b7e51 00000000f000d3c4
Fri Jul 20 07:39:14 noname.example.com lom: %l0-%l3: 0000000001833bf0 000003000007c1d8 0000000000000001 000003000007c1b0
Fri Jul 20 07:39:14 noname.example.com lom: %l4-%l7: 000003000007c200 0000000000000007 000000000000006d 0000000000000000
Fri Jul 20 07:39:14 noname.example.com lom: %i0-%i3: 0000000000000000 000000000180b880 00000000f05b7f01 0000000000000000
Fri Jul 20 07:39:14 noname.example.com lom: %i4-%i7: 0000000001038280 0000000000000000 000000000180ae71 00000000f000d3a0
Fri Jul 20 07:39:14 noname.example.com lom:
Fri Jul 20 07:39:14 noname.example.com lom: %cwp: 4
Fri Jul 20 07:39:15 noname.example.com lom: frame address (64-bit):000000000180b670
Fri Jul 20 07:39:15 noname.example.com lom: PC of call instruction:00000000f000d3a0
Fri Jul 20 07:39:15 noname.example.com lom: %o0-%o3: 0000000000000000 000000000180b880 00000000f05b7f01 0000000000000000
Fri Jul 20 07:39:15 noname.example.com lom: %o4-%o7: 0000000001038280 0000000000000000 000000000180ae71 00000000f000d3a0
Fri Jul 20 07:39:16 noname.example.com lom: %l0-%l3: 00000000000000bb 000000000000000f 000000000000000f 000002a1004e0000
Fri Jul 20 07:39:16 noname.example.com lom: %l4-%l7: 0000000000000000 0000000000000008 000000000180b7d8 0000000000008000
Fri Jul 20 07:39:16 noname.example.com lom: %i0-%i3: 0000000001836cb0 000000000180e000 0000000000000001 0000000000000001
Fri Jul 20 07:39:16 noname.example.com lom: %i4-%i7: 0000000000000000 0000000001836ca8 000000000180af21 0000000001016198
Fri Jul 20 07:39:16 noname.example.com lom:
Fri Jul 20 07:39:16 noname.example.com lom: %cwp: 3
Fri Jul 20 07:39:16 noname.example.com lom: frame address (64-bit):000000000180b720
Fri Jul 20 07:39:16 noname.example.com lom: PC of call instruction:0000000001016198
Fri Jul 20 07:39:16 noname.example.com lom: %o0-%o3: 0000000001836cb0 000000000180e000 0000000000000001 0000000000000001
Fri Jul 20 07:39:16 noname.example.com lom: %o4-%o7: 0000000000000000 0000000001836ca8 000000000180af21 0000000001016198
Fri Jul 20 07:39:16 noname.example.com lom: %l0-%l3: 00000000018b0190 00000000018b0000 0000000001829000 0000000000000000
Fri Jul 20 07:39:16 noname.example.com lom: %l4-%l7: 0000000000000001 0000000000000000 0000000000000000 0000000000000000
Fri Jul 20 07:39:16 noname.example.com lom: %i0-%i3: ffffffffffffffff 0000000000000000 0000000000000000 000000000180c000
Fri Jul 20 07:39:16 noname.example.com lom: %i4-%i7: 000000000180c000 0000000000000000 000000000180afd1 000000000104bd64
Fri Jul 20 07:39:17 noname.example.com lom:
Fri Jul 20 07:39:17 noname.example.com lom: %cwp: 2
Fri Jul 20 07:39:18 noname.example.com lom: frame address (64-bit):000000000180b7d0
Fri Jul 20 07:39:18 noname.example.com lom: PC of call instruction:000000000104bd64
Fri Jul 20 07:39:18 noname.example.com lom: %o0-%o3: ffffffffffffffff 0000000000000000 0000000000000000 000000000180c000
Fri Jul 20 07:39:18 noname.example.com lom: %o4-%o7: 000000000180c000 0000000000000000 000000000180afd1 000000000104bd64
Fri Jul 20 07:39:18 noname.example.com lom: %l0-%l3: 000000000000009b 00000000018c5400 000000000000009b 000000000182cc00
Fri Jul 20 07:39:18 noname.example.com lom: %l4-%l7: 000000000000009a 0000000000000010 000000000000009a 0000000000000001
Fri Jul 20 07:39:18 noname.example.com lom: %i0-%i3: 0000000000000000 0000000000000000 0000000000000000 0000000000000005
Fri Jul 20 07:39:18 noname.example.com lom: %i4-%i7: 0000000000000000 0000000000000000 fffffffffffff681 0000000000000000
Fri Jul 20 07:39:18 noname.example.com lom:
Fri Jul 20 07:39:18 noname.example.com lom: No secondary saved state available.
Fri Jul 20 07:39:18 noname.example.com lom:
Fri Jul 20 07:39:18 noname.example.com lom: {/N0/SB0/P1/C0}
Fri Jul 20 07:39:18 noname.example.com lom:Regular AlternateMMU Interrupt
Fri Jul 20 07:39:18 noname.example.com lom: %g1: 0000000000000000 <unavailable>00000000018859e8 0000000000000000
Fri Jul 20 07:39:18 noname.example.com lom: %g2: 0000000070002000 <unavailable>0000000000000004 0000000000000000
Fri Jul 20 07:39:18 noname.example.com lom: %g3: 0000030002338000 0000000000000031 0000000000000c55 0000000000000000
Fri Jul 20 07:39:18 noname.example.com lom: %g4: 000000000000000f ffffffffffffffff 0000000000038001 0000000000000000
Fri Jul 20 07:39:18 noname.example.com lom: %g5: 000002a1004dfcc0 000000000000000f 0000000000000414 0000000000000000
Fri Jul 20 07:39:20 noname.example.com lom: %g6: 0000000000000000 000000000100769c 000000000180e580 0000000000000000
Fri Jul 20 07:39:20 noname.example.com lom: %g7: 000002a1004dfcc0 1fd6fa00001ffe0e 0000000000000068 0000000000000000
Fri Jul 20 07:39:20 noname.example.com lom:
Fri Jul 20 07:39:20 noname.example.com lom: %pil: a
Fri Jul 20 07:39:20 noname.example.com lom:
Fri Jul 20 07:39:20 noname.example.com lom: %tick: 000000000022497b %tick_cmpr:8000000000000000
Fri Jul 20 07:39:20 noname.example.com lom: %sys_tick:000000008b880c17 %sys_tick_cmpr: ffffffffffffffff
Fri Jul 20 07:39:20 noname.example.com lom:
Fri Jul 20 07:39:20 noname.example.com lom: AFAR:0000000002e01730 AFSR:0010000200000128
Fri Jul 20 07:39:20 noname.example.com lom: AFAR_2: 0000000002e01730 AFSR_2: 0010000200000128
Fri Jul 20 07:39:20 noname.example.com lom:
Fri Jul 20 07:39:20 noname.example.com lom: Bank 0 MADR: 8001fe0000000100 Bank 1 MADR: 8001fe0000000500
Fri Jul 20 07:39:20 noname.example.com lom: Bank 2 MADR: 8001fe0000000900 Bank 3 MADR: 8001fe000000
