Is it possible to connect more than one Niagara processor to have a "multi-niagara" shared memory machine?
In other words: T1 has 8x4=32 hardware threads. Can I connect two of them to the same blade (or however it is) and then have 8x4x2=64 threads running in parallel?
Thank you very much in advance for answers.
Cristian Perfumo
> Is it possible to connect more than one Niagara processor to have a "multi-niagara" shared memory
> machine?In other words: T1 has 8x4=32 hardware threads. Can I connect two of them
> to the same blade (or however it is) and then have 8x4x2=64 threads running in parallel?
Cristian,
With the existing T1 (Niagara) design, the answer is "no" because, for one thing, no means of maintaining cache coherence between multiple processors was designed into T1.
However, adding cache coherence across chips would be a great enhancement that could be contributed to the OpenSPARC community!
Thank you, dweaver.
Last week I had a course with Kunle Olukotun and I told him my doubt. As you pointed out, T1 doesn't have (off chip) cache coherence and T2 won't have it either. The next generation (hi calls it T2+) will include it and allow more than one chip to share memory.
Okey, thank you very much for your answer and I hope what I'm writing complements it.
Cheers.
Cristian Perfumo
