V490: rscadm: RSC firmware not respondig
Hello,
The story starts when I have instlled the RSC package on Sol 10.
I'v runt the rsc-config script.... and after the process finished I wasn't able to login on the RSC (I still can't). What ever command I'm perdorming on OS (e.g. ./rscadm version) the response is:
rscadm: RSC firmware not responding
I've tried to reset and bellow You can find the output:
Welcome to RSC bootmon v2.2.2
Reset register: 40000000 ESRS
RSC2 POST - Version 10-18-2000 0.7
Dual Port Memory Test, PASSED.
TTY External - Internal Loopback Test
TTY External - Internal Loopback Test, PASSED.
TTYC - Internal Loopback Test
TTYC - Internal Loopback Test, PASSED.
TTYD - Internal Loopback Test
TTYD - Internal Loopback Test, PASSED.
Memory Data Lines Test
Memory Data Lines Test, PASSED.
Memory Address Lines Test
Slide address bits to test open address lines
Testfor shorted address lines
Memory Address Lines Test, PASSED.
Boot Sector FLASH CRC Test
Boot Sector FLASH CRC Test, PASSED.
Return to Boot Monitorfor Handshake
RSC2 POST - Version 10-18-2000 0.7Status = 00007fff
Returned from Boot Monitor and Handshake
Instruction CACHE Test
DISABLE the I-CACHE
ENABLE the I-CACHE
Verify I-CACHE Performance Increase
Instruction CACHE Test, PASSED.
Memory Cells Test
Counting UP:Write data: 00000000
Counting DOWN: Read - Verify - Write data: ffffffff
Counting UP:Read - Verify - Write data: 55aa33cc
Counting DOWN: Read - Verify - Write data: aa33cc66
Counting UP:Read - Verify - Write data: 33cc6699
Counting DOWN: Read - Verify - Write data: cc669955
Counting UP:Read - Verify - Write data: 669955aa
Counting DOWN: Read - Verify - Write data: 9955aa33
Counting UP:Read - Verify - Write data: f0f0f0f0
Memory Cells Test, PASSED.
Data CACHE Test
Verify D-CACHE Performance Increase
D-CACHE Performance Increase I-CACHE Disabled
D-CACHE Performance Increase I-CACHE Enabled
Verify D-CACHE Memory
Data CACHE Test, PASSED.
Main Sectors FLASH CRC Test
ERROR: RSC POST TEST
H/W under test= Flash Memory Data
Test name= FLASH CRC Test
Subtest name = Main Sector Flash Test
Failure: CRC Error - ReFlash EPROM.
EPROM CRC: 98a2bebb Calced CRC: 20e2c3d3
END_ERROR
Main Sectors FLASH CRC Test, FAILED.
Load the RSC, then 鶦opying self to RAM...Done.
Jumping to RAM.
Waitingfor boot protocol message...
Did not get a boot protocol message.
RSC <ESC> Menu
f - Waitfor flash download from host.
C - Copy Boot Monitor from FLASHBOAT.
j - Jump to main code (at 0x01010000).
m - Run POST Menu.
(Do nottrythis after a flash update of the boot monitor!)
d - play DOOM
s - Set clock speed
e - Set external serial ports baud rate
i - Set internal serial ports baud rate
t - Toggle'OK' flag
R - Reset RSC
b,h,w - Read byte/halfword/word
B,H,W - Write byte/halfword/word
r - Return to bootmon
Your selection:
SC <ESC> Menu
f - Waitfor flash download from host.
C - Copy Boot Monitor from FLASHBOAT.
j - Jump to main code (at 0x01010000).
m - Run POST Menu.
(Do nottrythis after a flash update of the boot monitor!)
d - play DOOM
s - Set clock speed
e - Set external serial ports baud rate
i - Set internal serial ports baud rate
t - Toggle'OK' flag
R - Reset RSC
b,h,w - Read byte/halfword/word
B,H,W - Write byte/halfword/word
r - Return to bootmon
Your selection: f
Copying self to RAM...Done.
Jumping to RAM.
Waitingfor boot protocol message...
Welcome to RSC bootmon v2.2.2
Reset register: e8000000 EHRS ESRS LLRS CSRS
RSC2 POST - Version 10-18-2000 0.7
Dual Port Memory Test, PASSED.
TTY External - Internal Loopback Test
TTY External - Internal Loopback Test, PASSED.
TTYC - Internal Loopback Test
TTYC - Internal Loopback Test, PASSED.
TTYD - Internal Loopback Test
TTYD - Internal Loopback Test, PASSED.
Memory Data Lines Test
Memory Data Lines Test, PASSED.
Memory Address Lines Test
Slide address bits to test open address lines
Testfor shorted address lines
Memory Address Lines Test, PASSED.
Boot Sector FLASH CRC Test
Boot Sector FLASH CRC Test, PASSED.
Return to Boot Monitorfor Handshake
RSC2 POST - Version 10-18-2000 0.7Status = 00007fff
Returned from Boot Monitor and Handshake
Instruction CACHE Test
DISABLE the I-CACHE
ENABLE the I-CACHE
Verify I-CACHE Performance Increase
Instruction CACHE Test, PASSED.
Memory Cells Test
Counting UP:Write data: 00000000
Counting DOWN: Read - Verify - Write data: ffffffff
Counting UP:Read - Verify - Write data: 55aa33cc
Counting DOWN: Read - Verify - Write data: aa33cc66
Counting UP:Read - Verify - Write data: 33cc6699
Counting DOWN: Read - Verify - Write data: cc669955
Counting UP:Read - Verify - Write data: 669955aa
Counting DOWN: Read - Verify - Write data: 9955aa33
Counting UP:Read - Verify - Write data: f0f0f0f0
Memory Cells Test, PASSED.
Data CACHE Test
Verify D-CACHE Performance Increase
D-CACHE Performance Increase I-CACHE Disabled
D-CACHE Performance Increase I-CACHE Enabled
Verify D-CACHE Memory
Data CACHE Test, PASSED.
Main Sectors FLASH CRC Test
ERROR: RSC POST TEST
H/W under test= Flash Memory Data
Test name= FLASH CRC Test
Subtest name = Main Sector Flash Test
Failure: CRC Error - ReFlash EPROM.
EPROM CRC: 98a2bebb Calced CRC: 20e2c3d3
END_ERROR
Main Sectors FLASH CRC Test, FAILED.
Load the RSC, then 鶦opying self to RAM...Done.
Jumping to RAM.
Waitingfor boot protocol message...
Did not get a boot protocol message.
RSC <ESC> Menu
f - Waitfor flash download from host.
C - Copy Boot Monitor from FLASHBOAT.
j - Jump to main code (at 0x01010000).
m - Run POST Menu.
(Do nottrythis after a flash update of the boot monitor!)
d - play DOOM
s - Set clock speed
e - Set external serial ports baud rate
i - Set internal serial ports baud rate
t - Toggle'OK' flag
R - Reset RSC
b,h,w - Read byte/halfword/word
B,H,W - Write byte/halfword/word
r - Return to bootmon
Your selection: C
Configure the jumper to read from FLASHBOAT, hit'c' tocontinue Welcome to RSC bootmon v2.2.2
Reset register: e8000000 EHRS ESRS LLRS CSRS
RSC2 POST - Version 10-18-2000 0.7
Dual Port Memory Test, PASSED.
TTY External - Internal Loopback Test
TTY External - Internal Loopback Test, PASSED.
TTYC - Internal Loopback Test
TTYC - Internal Loopback Test, PASSED.
TTYD - Internal Loopback Test
TTYD - Internal Loopback Test, PASSED.
Memory Data Lines Test
Memory Data Lines Test, PASSED.
Memory Address Lines Test
Slide address bits to test open address lines
Testfor shorted address lines
Memory Address Lines Test, PASSED.
Boot Sector FLASH CRC Test
Boot Sector FLASH CRC Test, PASSED.
Return to Boot Monitorfor Handshake
RSC2 POST - Version 10-18-2000 0.7Status = 00007fff
Returned from Boot Monitor and Handshake
Instruction CACHE Test
DISABLE the I-CACHE
ENABLE the I-CACHE
Verify I-CACHE Performance Increase
Instruction CACHE Test, PASSED.
Memory Cells Test
Counting UP:Write data: 00000000
Counting DOWN: Read - Verify - Write data: ffffffff
Counting UP:Read - Verify - Write data: 55aa33cc
Counting DOWN: Read - Verify - Write data: aa33cc66
Counting UP:Read - Verify - Write data: 33cc6699
Counting DOWN: Read - Verify - Write data: cc669955
Counting UP:Read - Verify - Write data: 669955aa
Counting DOWN: Read - Verify - Write data: 9955aa33
Counting UP:Read - Verify - Write data: f0f0f0f0
Memory Cells Test, PASSED.
Data CACHE Test
Verify D-CACHE Performance Increase
D-CACHE Performance Increase I-CACHE Disabled
D-CACHE Performance Increase I-CACHE Enabled
Verify D-CACHE Memory
Data CACHE Test, PASSED.
Main Sectors FLASH CRC Test
ERROR: RSC POST TEST
H/W under test= Flash Memory Data
Test name= FLASH CRC Test
Subtest name = Main Sector Flash Test
Failure: CRC Error - ReFlash EPROM.
EPROM CRC: 98a2bebb Calced CRC: 20e2c3d3
END_ERROR
Main Sectors FLASH CRC Test, FAILED.
Load the RSC, then 鶦opying self to RAM...Done.
Jumping to RAM.
Waitingfor boot protocol message...
Did not get a boot protocol message.
RSC <ESC> Menu
f - Waitfor flash download from host.
C - Copy Boot Monitor from FLASHBOAT.
j - Jump to main code (at 0x01010000).
m - Run POST Menu.
(Do nottrythis after a flash update of the boot monitor!)
d - play DOOM
s - Set clock speed
e - Set external serial ports baud rate
i - Set internal serial ports baud rate
t - Toggle'OK' flag
R - Reset RSC
b,h,w - Read byte/halfword/word
B,H,W - Write byte/halfword/word
r - Return to bootmon
Your selection: d
OK. You're DOOMED!
RSC <ESC> Menu
f - Waitfor flash download from host.
C - Copy Boot Monitor from FLASHBOAT.
j - Jump to main code (at 0x01010000).
m - Run POST Menu.
(Do nottrythis after a flash update of the boot monitor!)
d - play DOOM
s - Set clock speed
e - Set external serial ports baud rate
i - Set internal serial ports baud rate
t - Toggle'OK' flag
R - Reset RSC
b,h,w - Read byte/halfword/word
B,H,W - Write byte/halfword/word
r - Return to bootmon
Your selection: f
Copying self to RAM...Done.
Jumping to RAM.
Waitingfor boot protocol message...
Welcome to RSC bootmon v2.2.2
Reset register: e8000000 EHRS ESRS LLRS CSRS
RSC2 POST - Version 10-18-2000 0.7
Dual Port Memory Test, PASSED.
TTY External - Internal Loopback Test
TTY External - Internal Loopback Test, PASSED.
TTYC - Internal Loopback Test
TTYC - Internal Loopback Test, PASSED.
TTYD - Internal Loopback Test
TTYD - Internal Loopback Test, PASSED.
Memory Data Lines Test
Memory Data Lines Test, PASSED.
Memory Address Lines Test
Slide address bits to test open address lines
Testfor shorted address lines
Memory Address Lines Test, PASSED.
Boot Sector FLASH CRC Test
Boot Sector FLASH CRC Test, PASSED.
Return to Boot Monitorfor Handshake
RSC2 POST - Version 10-18-2000 0.7Status = 00007fff
Returned from Boot Monitor and Handshake
Instruction CACHE Test
DISABLE the I-CACHE
ENABLE the I-CACHE
Verify I-CACHE Performance Increase
Instruction CACHE Test, PASSED.
Memory Cells Test
Counting UP:Write data: 00000000
Counting DOWN: Read - Verify - Write data: ffffffff
Counting UP:Read - Verify - Write data: 55aa33cc
Counting DOWN: Read - Verify - Write data: aa33cc66
Counting UP:Read - Verify - Write data: 33cc6699
Counting DOWN: Read - Verify - Write data: cc669955
Counting UP:Read - Verify - Write data: 669955aa
Counting DOWN: Read - Verify - Write data: 9955aa33
Counting UP:Read - Verify - Write data: f0f0f0f0
Memory Cells Test, PASSED.
Data CACHE Test
Verify D-CACHE Performance Increase
D-CACHE Performance Increase I-CACHE Disabled
D-CACHE Performance Increase I-CACHE Enabled
Verify D-CACHE Memory
Data CACHE Test, PASSED.
Main Sectors FLASH CRC Test
ERROR: RSC POST TEST
H/W under test= Flash Memory Data
Test name= FLASH CRC Test
Subtest name = Main Sector Flash Test
Failure: CRC Error - ReFlash EPROM.
EPROM CRC: 98a2bebb Calced CRC: 20e2c3d3
END_ERROR
Main Sectors FLASH CRC Test, FAILED.
Load the RSC, then 鶦opying self to RAM...Done.
Jumping to RAM.
Waitingfor boot protocol message...
Did not get a boot protocol message.
RSC <ESC> Menu
f - Waitfor flash download from host.
C - Copy Boot Monitor from FLASHBOAT.
j - Jump to main code (at 0x01010000).
m - Run POST Menu.
(Do nottrythis after a flash update of the boot monitor!)
d - play DOOM
s - Set clock speed
e - Set external serial ports baud rate
i - Set internal serial ports baud rate
t - Toggle'OK' flag
R - Reset RSC
b,h,w - Read byte/halfword/word
B,H,W - Write byte/halfword/word
r - Return to bootmon
Your selection: j
Welcome to RSC bootmon v2.2.2
Reset register: e8000000 EHRS ESRS LLRS CSRS
RSC2 POST - Version 10-18-2000 0.7
Dual Port Memory Test, PASSED.
TTY External - Internal Loopback Test
TTY External - Internal Loopback Test, PASSED.
TTYC - Internal Loopback Test
TTYC - Internal Loopback Test, PASSED.
TTYD - Internal Loopback Test
TTYD - Internal Loopback Test, PASSED.
Memory Data Lines Test
Memory Data Lines Test, PASSED.
Memory Address Lines Test
Slide address bits to test open address lines
Testfor shorted address lines
Memory Address Lines Test, PASSED.
Boot Sector FLASH CRC Test
Boot Sector FLASH CRC Test, PASSED.
Return to Boot Monitorfor Handshake
RSC2 POST - Version 10-18-2000 0.7Status = 00007fff
Returned from Boot Monitor and Handshake
Instruction CACHE Test
DISABLE the I-CACHE
ENABLE the I-CACHE
Verify I-CACHE Performance Increase
Instruction CACHE Test, PASSED.
Memory Cells Test
Counting UP:Write data: 00000000
Counting DOWN: Read - Verify - Write data: ffffffff
Counting UP:Read - Verify - Write data: 55aa33cc
Counting DOWN: Read - Verify - Write data: aa33cc66
Counting UP:Read - Verify - Write data: 33cc6699
Counting DOWN: Read - Verify - Write data: cc669955
Counting UP:Read - Verify - Write data: 669955aa
Counting DOWN: Read - Verify - Write data: 9955aa33
Counting UP:Read - Verify - Write data: f0f0f0f0
Memory Cells Test, PASSED.
Data CACHE Test
Verify D-CACHE Performance Increase
D-CACHE Performance Increase I-CACHE Disabled
D-CACHE Performance Increase I-CACHE Enabled
Verify D-CACHE Memory
Data CACHE Test, PASSED.
Main Sectors FLASH CRC Test
ERROR: RSC POST TEST
H/W under test= Flash Memory Data
Test name= FLASH CRC Test
Subtest name = Main Sector Flash Test
Failure: CRC Error - ReFlash EPROM.
EPROM CRC: 98a2bebb Calced CRC: 20e2c3d3
END_ERROR
Main Sectors FLASH CRC Test, FAILED.
Load the RSC, then 鶦opying self to RAM...Done.
Jumping to RAM.
Waitingfor boot protocol message...
[there is some interraction with the RSC, the menu was displayed and I have tried some functions.]
I've been googling and I have found that it is possible to download firmware image to the RSC, so the next step was to do it:
./rscadm download usr/platform/`uname -i`/lib/images/rscfw
rscadm: RSC did not respond during boot initialization
The download subcommand for rscadm has oprion "boot" but i couldn't find anywhere proper image :(. So If You know when it can be found I will be thankfull.
Maybe You have some other ideas how to fix it?
Regards and thanx in advance
toostrow
