what is the reason for rollback
Dear all:
I have read OpenSPARCT1_Micro_Arch.pdf. But when I read about"2.3.13Rollback Mechanism", I could not catch the
meaning.
I have some idea about rollback, but not sure.
I think, the reason that rollback exists is that a thread must be stall for some reason after D stage,
but the stage for thread to switch in must be F or S stage. So thread must rollback to F or S stage, until then, it
can be switched out and wait for next scheduling.
Is it right? Can anyone help me?
Thanks
[543 byte] By [
atlargea] at [2007-11-27 5:20:46]
# 1
The rollback described in this section is simply resetting the fetch unit to fetch from the correct address following a stall.
For example: Suppose the fetch unit fetches a new instruction for a thread from address 0x100 at cycle 0. On the next cycle, this instruction will be at S stage, and the fetch unit will be fetching the next instruction from address 0x104. On the third cycle, the first instruction will be in stage D, and the fetch unit will be fetching the third instruction from address 0x108.
Now if the first instruction hits a stall condition in stage E, then the first instruction, according to the document, will be returned to the S stage of the pipeline. In addition, the program counter for the thread must be reset to fetch from the proper address so that all instructions are executed in the proper order.
Think of the pipeline being 4-threads wide in the F and S stages. At the end of the S stage is a multiplexor which selects the thread to issue to the D stage. The rest of the pipeline is only one thread wide. The goal is to keep the later stages of the pipeline busy as much as possible. The fetch unit will fetch instructions for all threads and place them in the instruction buffer (stage S). The instructions will wait in stage S until the thread-switch logic selects that thread. When that thread is selected, the instructions will proceed down the pipeline. Now suppose a load is issued for thread 0, followed by another instruction for the same thread.If in stage M the load misses, then the second instruction cannot complete, so it is flushed from the pipeline, and returned to stage S. In addition, the thread-switch logic will then pick a different thread to issue to the D stage in the next cycle.
Does this help?
