[Need Help]T1 EDA simulation ERROR
Hi everyone
I was trying to run T1 RTL simulation in Linux/i686 platform, using NC-verilog as simulation tools
I have rebuilt the pli by using "mkplilib ncverilog",
new "ncsim" and "ncelib" has been created in $DV_ROOT/tools/Linux/i686
I run the sims under the command
"sims -sim_type=ncv -novera_build -novera_run -group=core1_mini"
but get so many warning and an Error during the simulation
the tail of sims.log:
sims -sim_type=ncv -novera_build -novera_run -group=core1_mini
ncvlog: *W,UNBINS: Unbound instance found: flop_rptrs::bw_clk_gl_rstce_rtl in unit worklib.OpenSPARCT1:v.
ncvlog: *E,UNBERR: (9561) unbound instance(s).
Total errors/warnings found outside modules and primitives:
errors: 1, warnings: 9723
ncverilog: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 1).
sims: Caught a SIGDIE. failed building model at /home/tyx/SPARC/OpenSPARC-T1/v1.4/tools/src/sims/sims,1.262 line 2218.
sims: Caught a SIGDIE. Could not build model for regression at /home/tyx/SPARC/OpenSPARC-T1/v1.4/tools/src/sims/sims,1.262 line 1272.
has anyone seen this error before?
any solution?
