Hello guys,
Could someone point me how Solaris 8 (and Solaris 10 if is there any difference) uses the RAM memory when a multiprocessor machine
is in place (for example 4 CPUs).
As an example: I have 32 GB RAM and 4 CPUs, should I
expect to use 8GB per CPU or is totally dynamic based on process
requirements ?
Any doc explaining this ?
Thanks
Its all completely dynamic.
Most multiprocessor machines with reasonable numbers of processors (and all that sun sells)
are hardware SMP. Thats stands for symmetric multiprocessing.
What that means is that all memory is the same as far as each CPU is concerned.
So theres no memory in general set aside for a particular CPU.
Any CPU can use any memory. And any process can run on any CPU.
And a process in general can bounce dynamically around between CPU's.
Look up SMP in google or wikipedia...
> As an example: I have 32 GB RAM and 4 CPUs, should I
> expect to use 8GB per CPU or is totally dynamic based
> on process
> requirements ?
It's dynamic. Memory is allocated to processes as needed (and used for various buffers when not otherwise needed). Runnable threads are allocated to CPUs by the scheduler. There's no particular relationship between the two. So you might have one process with most of your memory, and a few a few other processes using only small amounts of memory. Theyll all get CPU time as needed.
> Any doc explaining this ?
I can't think of a document on exactly that topic. There's developer information on both the scheduler and on memory management in various detail.
--
Darren
Well, I'd agree with the above, but there are exceptions with certain kinds of hardware, for example the V210/V240 seems to allocate memory per CPU, if you put DIMMS in the sockets for CPU1 they won't be accessible by CPU0.
Also there are some other platforms where you can tell the system to interleave memory or not, meaning if you want CPUs to be able to allocate memory on other boards.
For the highend SPARC systems there is a new feature in Solaris 10 (Memory Placement Optimization; see infodoc 76905) which tries to optimize the memory allocation so that a process gets memory on the nearby DIMMs, this is to avoid the latency which occurs if a process running on one systemboard allocates memory on a different system board.
.7/M.
> Well, I'd agree with the above, but there are
> exceptions with certain kinds of hardware, for
> example the V210/V240 seems to allocate memory per
> CPU, if you put DIMMS in the sockets for CPU1 they
> won't be accessible by CPU0.
There are several Sun NUMA machines (210/240 among them) where CPUs have differing amounts of latency to particular areas of memory, but none that I'm aware of where CPUs have only partial views of memory.
I do not believe that memory in CPU1 sockets is inaccessible by CPU0.
If MPO is in effect, there might be some desire to allocate some memory other other based on the CPU/group in use, but this is only a preference, not a restriction.
Otherwise a particular process could not have ncpu threads running simultanously (because some CPUs could not see the process contents), nor could a single process allocate most of the memory in the box (because no single CPU could access it).
> Also there are some other platforms where you can
> tell the system to interleave memory or not, meaning
> if you want CPUs to be able to allocate memory on
> other boards.
Correct, but all the memory is still visible by all CPUs. There is no restriction imposed on where a process may run based on RAM (although there may be an preference for particular CPUs to reduce latency).
> For the highend SPARC systems there is a new feature
> in Solaris 10 (Memory Placement Optimization; see
> infodoc 76905) which tries to optimize the memory
> allocation so that a process gets memory on the
> nearby DIMMs, this is to avoid the latency which
> occurs if a process running on one systemboard
> allocates memory on a different system board.
Exactly. So this isn't an exception, it's an enhancement or optimization.Without MPO in place, the hardware still acts the same, but most functions of the kernel assume a single-layer memory model when allocating RAM and scheduling CPUs and everything still works.
My phrase about "no particular relationship between the two" would be incorrect if MPO were in use.
--
Darren
> There are several Sun NUMA machines (210/240 among
> them) where CPUs have differing amounts of latency to
> particular areas of memory, but none that I'm aware
> of where CPUs have only partial views of memory.
>
> I do not believe that memory in CPU1 sockets is
> inaccessible by CPU0.
True, perhaps its just a memory controller issue, if you fill all sockets in a V240 but only have 1 CPU you will only see the memory in the sockets belonging to that CPU.
.7/M.
