hi all:
Help me!
When I synthesis the sparc core1 code,I found that description in cluster_head module(cluster_head.v) like:
assign #10 rclk = gclk&sync_enable;
why add #10 delay?Just for timing test or it's used for adjust the clk phase?Is it useful?
Is there any problem when I omit this #10 delay during synthesis the code?
Thanks in advance!
The #10 delay is most likely only used during RTL verification to
simulate approximate transport delays for the rclk signal.
The synthesizer ignores all the timing control (delays etc) in RTL
when synthesizing RTL into a gate netlist. The synthesizer's gate
netlist is based purely on the constraints (timing, power and area
that you provide it with, to achive gate netlist closure)
Sincerely,
-
Taha Amiralli
thamiral [A] uwo [D] ca
thamiral [A] gmail [D] com
MESc Candidate 2007, Computer Engineering
The University Of Western Ontario
BESc, BSc. 2005,
Computer Engineering & Computer Science
The University Of Western Ontario
On 12/25/06, general@opensparc.info <general@opensparc.info> wrote:
> hi all:
>Help me!
>
> When I synthesis the sparc core1 code,I found that description in cluster_head module(cluster_head.v) like:
>
>assign #10 rclk = gclk&sync_enable;
>
> why add #10 delay?Just for timing test or it's used for adjust the clk phase?Is it useful?
>
> Is there any problem when I omit this #10 delay during synthesis the code?
>
> Thanks in advance!
>
>
> To unsubscribe, e-mail: general-unsubscribe@opensparc.sunsource.net
> For additional commands, e-mail: general-help@opensparc.sunsource.net
>
>
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