Verilog HDL Programming.
[228 byte] By [Raghuram] at [2007-11-26 11:26:48] 
Can anyone suggest me how to implement a "64:5 Multiplexer using 6 select lines"?I mean selecting only five signals from the incoming 64 signals.Can anyone suggest a Verilog RTL Implementation for it?
# 1
I thought you can use "case" condition to select 5 signals from 64.junwu at 2007-7-7 3:42:22 >
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