RTL: regular version vs FPGA version

In the T1 RTL code, there are FPGA version and regular version in many blocks. My question is, are these versions functionally identical? Do they have the same timing? If I want to implement T1 core by selecting regular versions of the RTL code in some blocks and FPGA versions of the RTL code in other blocks, would the new T1 still be functiional?

[356 byte] By [txu] at [2007-11-26 11:09:51]