A question came up recently about the availability of a cycle-accurate simulator for OpenSPARC T1.
It may not have been well -publicized, but the SESC simulator from community member UC Santa Cruzdoes provide cycle-accurate simulation. See http://www.opensparc.net/component/option,com_mtree/task,viewlink/link_id,8/ for more information.
SESC is actually a MIPS simulator. As far as I understood it is possible to feed trace from T1 functional simulator to SESC and get some idea about timing. However, this would be inefficient. Accuracy is also not clear.
It would be much easier to run native T1 simulator and be able to modify model for architectural experimentation. It seems strange that Sun disclosed RTL but not timing simulator.
>SESC is actually a MIPS simulator.
SESC is ISA independent, but the only execution-driven simulation supported at sourceforge is MIPS. It can read traces from SPARC and PPC.
>As far as I understood it is possible to feed trace from T1 functional simulator to SESC
Yes, you can generate RST traces from SAM and feed them to SESC.
> and get some idea about timing. However, this would be inefficient. Accuracy is also not clear.
SESC is a traditional architectural simulator like simplescalar or RSIM or GEMs. All these simulators are "relatively" fast. Of course, they do tradeoffs between accuracy and simulation speed.
