E4500 Online/failure Clock Board HOTPLUG_LOGIC
Hi all Gurus,
How to enable the clock board.
Thanks
Andry
reset-all
Resetting...
Software Power ON
@(#) Ultra Enterprise 3.2 Version 25 created 2000/03/29 14:52
CPU = 0000.0000.0000.0000
Probing keyboard Done
0,0>
0,0>@(#) POST 3.9.25 2000/03/29 14:56
0,1>
0,0>Copyright 2000 Sun Microsystems, Inc. All rights reserved.
0,1>@(#) POST 3.9.25 2000/03/29 14:56
0,0>
SelfTest Initializing (Diag Level 10, ENV 00004001) IMPL 0011 MASK 20
0,1>Copyright 2000 Sun Microsystems, Inc. All rights reserved.
0,0>Board 0 CPU FPROM Test
0,1>
SelfTest Initializing (Diag Level 10, ENV 00000000) IMPL 0011 MASK 20
0,0>Board 0 Basic CPU Test
0,0>Set CPU UPA Config and Init SDB Data
0,0>SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0
0,0>Board 0 MMU Enable Test
0,0>DMMU Init
0,0>IMMU Init
0,0>Mapping Selftest Enabling MMUs
0,0>Board 0 Ecache Test
0,0>Ecache Probe
0,0>Ecache Tags
0,1>Board 0 CPU FPROM Test
0,1>Board 0 Basic CPU Test
0,1>Set CPU UPA Config and Init SDB Data
0,1>SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0
0,1>Board 0 MMU Enable Test
0,1>DMMU Init
0,1>IMMU Init
0,1>Mapping Selftest Enabling MMUs
0,1>Board 0 Ecache Test
0,1>Ecache Probe
0,1>Ecache Tags
0,0>Ecache Quick Verify
0,1>Ecache Quick Verify
0,0>Ecache Init
0,1>Ecache Init
0,0>Ecache RAM
0,1>Ecache RAM
0,0>Ecache Address Line
0,0>Configure Ecache Limit
0,0>Ecache Size = 00400000, Limited to 00400000
0,0>Board 0 FPU Functional Test
0,0>FPU Enable
0,0>Board 0 Board Master Select Test
0,0>Selecting a Board Master
0,0>Board 0 FireHose Devices Test
0,1>Ecache Address Line
0,1>Configure Ecache Limit
0,1>Ecache Size = 00400000, Limited to 00400000
0,1>Board 0 FPU Functional Test
0,1>FPU Enable
0,1>Board 0 Board Master Select Test
0,1>Selecting a Board Master
0,0>Board 0 Address Controller Test
0,0>AC Initialization
0,0>AC DTAG Init
0,0>Board 0 Dual Tags Test
0,0>AC DTAG Init
0,0>Board 0 FireHose Controller Test
0,0>FHC Initialization
0,0>Board 0 JTAG Test
0,0>Verify System Board Scan Ring
0,0>Board 0 Centerplane Test
0,0>Centerplane Join
0,0>Setting JTAG Master
0,0>Clear JTAG Master
0,0>Board 0 Setup Cache Size Test
0,0>Setting Up Cache Size
0,0>Board 0 System Master Select Test
0,0>Setting System Master
0,0>POST Master Selected (JTAG,CENTRAL)
0,0>Board 16 Clock Board Test
0,0>Clock Board Initialization
0,0>Clock Board Temperature Check
0,0>Board 16 Clock Board Serial Ports Test
0,0>Board 16 NVRAM Devices Test
0,0>M48T59 (TOD) Init
0,0>Board 0 System Board Probe Test
0,0>Probing all CPU/Memory BDA
0,0>Probing System Boards
0,0>Probing CPU Module JTAG Rings
0,0>Setting System Clock Frequency
0,0>CPU Module mid 0 Checked in OK (speed code = 7)
0,0>CPU mid 1 Version=00170011.20000507
0,0>CPU Module mid 1 Checked in OK (speed code = 7)
0,0>System Frequency (MHz),fcpu=336, fmod=168, fsys=84, fgen=336
0,0>Re-mapping to Local Device Space
0,0>Begin Central Space Serial Port access
0,0>Enable AC Control Parity
0,0>CenterPlane Signal Trigger is asserted. NO HOTPLUG
0,0>Board 0 Cross Calls Test
0,0>Board 0 Environmental Probe Test
0,0>Environmental Probe
0,0>Checking Power Supply Configuration
0,0>Power is more than adequate, load 1 ps 3
0,0>Use existing memory configuraton
0,0>Probing for Disk System boards
0,0>Board 0 System Interrupts Test
0,0>POST Failed
0,0>
0,0>System Board Status
0,0>--
0,0> SlotBoard StatusBoard TypeFailures
0,0>--
0,0> 0 | Normal |+CPU/Memory |
0,0> 1 | Not installed | |
0,0> 2 | Not installed | |
0,0> 3 | Not installed | |
0,0> 4 | Not installed | |
0,0> 5 | Not installed | |
0,0> 6 | Not installed | |
0,0> 7 | Not installed | |
0,0> 16 | Online/failure | Clock Board | HOTPLUG_LOGIC
0,0>--
0,0>
0,0>CPU Module Status
0,0>--
0,0> MID OK Cache SpeedVersion
0,0>--
0,0> 0 | y | 4096 | 336 | 00170011.20000507
0,0> 1 | y | 4096 | 336 | 00170011.20000507
0,0>--
0,0>System Frequency (MHz),fcpu=336, fmod=168, fsys=84, fgen=336
0,0>Populated Memory Bank Status
0,0>bd #SizeAddressWayStatus
0,0>0102400Normal
0,0>
0,0>
POST COMPLETE
0,0>Entering OBP
Switching to high addresses
Setting up TLBs Done
MMU ON
PC = 0000.01ff.f000.1cb8
PC = 0000.0000.0000.1d24
Decompressing in Memory Done
Size = 0000.0000.0006.c8f0
ttya initialized
Using POST's System Configuration
Setting up memory
Starting CPU ID 1
Clock board TOD does not match TOD on any IO board.
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II
:227: Device not found
ok
