number of irf (integer register file) reading ports, 3 or 4?
All T1 documents indicate that irf (integer register file) has 3 reading ports. But when reading through its rtl model bw_r_irf.v, I have to raise the doubt that it actually has 4 reading ports physically, which are r1, r2, r3 and r3h. Even though the addresses of r3 and r3h are very close, they are different by the lowest bit in the rtl. In physical implementation, you have to use a different ports for different addresses. So my question is:
1. Is T1 irf implemented with 4 ports physically or I miss-understand the problem?
2. What's the use for that extra port 3h?
[591 byte] By [
jwai] at [2007-11-26 10:54:41]
# 1
Hello Jwai,
Here is a response to your question from one of the T1 designers -
-
The 4th port is really tied to one of the other
3 ports. One of the ports is 128b wide instead
of 64b. This allows a store-double inst to be issued
in a cycle as the 4th port provides 2x64b, which are
merged into a 64b datum.
-
Regards,
Durgam.
# 2
One correction from an earlier post - Fourth port (rs3h) is tied to rs3 for the double-word store. The size of this datum is 96b (not 128b, as indicated in the previous post). rs3 provides lower 64b of the datum and rs3h provides bits [95:64] of the datum.Durgam.
# 3
Thanks for your reply, I think I understand the problem now. But I still need to confirm that:
The register file is implemented such that, when doing a read, only 4 high bits of the address got decoded, so content of two neighboring register got read out. For port 1 and 2, the lowerst bit of the address is used to select which one goes to the output. However for port3, the lowerst bit of the address is not used(even thouth it exists in RTL), so the content of both registers goes to the output, the data from the even register goes to port 3 while the data from the odd register goes to port 3h. And this scheme implies the architecture can guarantee that the lowerst bit of the address for read port 3 is always '0.
Is that right?
Thanks a lot
jwai at 2007-7-7 3:07:38 >
# 4
Hi,
--
The register file is implemented such that, when doing a read, only 4 high bits of the address got decoded, so content of two neighboring register got read out. For port 1 and 2, the lowerst bit of the address is used to select which one goes to the output.
--
RTL for port rs1, rs2 and rs3 are identical but implementation could be how you describe above. ie. using lowest bit of address to mux select which output goes out.
--
However for port3, the lowerst bit of the address is not used(even thouth it exists in RTL), so the content of both registers goes to the output, the data from the even register goes to port 3 while the data from the odd register goes to port 3h
--
All five bits of address are used for port3 in RTL, lowest bit is hardcoded to 1 for the port 3h. For double-store the lowest bit has to be zero (double word/even register alignment). For single word store, port3 can access either odd or even address (same mechanism as port1 and port2) and lower 32bits of port3 will be the same as port3h.
Thanks.
