Is there anywhere I can read more about the S1 specification? Like how many physical pins were used on the package. From the rtl, S1 should have 270 signal pins. Adding on power and other misc test pins, this will make S1 have around 500 pins. Will this be a rather expensive package for a rather small chip? Also, we are interested to see how much power S1 draw, and at what frequency does S1 run at. Thanks,
James
Hi James,
questions about the S1 Core should be posted on the s1 project page at http://s1.sunsource.net but I'll answer anyway.
You are right about the 270 ports of the s1_top module, but you should take into account that the S1 Core should be used into a system-on-a-chip and many ports are used just inside the SoC.
For instance all the Wishbone signals are used to connect to other Wishbone-compliant cores on the chip, and most (if not all) interrupt lines will just connect to other cores internal to the chip itself.
We plan to release a complete system-on-a-chip reference design based upon the S1, for instance the first one could be called S1-SOC1, where the top-level pins will just be system signals (clock, reset), interface with SRAM/DRAM memory (as usual) and some GPIO pins for software interaction with interfaces still unsupported in hardware.
About area and performances: the area of the S1 Core will be about the same of one single SPARC Core of the OpenSPARC T1, since our Wishbone bridge is very small if compared with the CPU; about performances we target a maximum working frequency of 500 MHz that should ideal for many embedded applications.
Cheers,
Fabrizio
