some synthesis problems

hi,

I use Synplify pro to synthesis the sparc module.

It gives me some error informations.

how could them occur?

what can I do?

@E: CL172 :"E:\sparcsyn\bw_r_rf32x152b.v":64:16:64:25|Only one always block may assign a given variable local_dout[151:0]

@E: CL172 :"E:\sparcsyn\bw_r_rf32x80.v":72:12:72:18|Only one always block may assign a given variable tsa_mem_0_[79:0]

@E: CL172 :"E:\sparcsyn\bw_r_tlb.v":188:12:188:24|Only one always block may assign a given variable tlb_entry_vld[63:0]

[537 byte] By [rockma] at [2007-11-26 8:59:14]