I'm working on timing closure of one sparc core.
It seems there are so many multicycle paths.
Any document available whcih has the list of
multicycle/false paths.
to one sparc core, three clock i/ps are present.
1.gclk > 1200 Mhz
2.efc_spc_fuse_clk1 > 240 Mhz
3.efc_spc_fuse_clk2 > 240 Mhz.
Also help me , if I have made any wrong assumptions
regarding the clock info. mentioned above.
Hello All,
The clocks efc_spc_fuse_clk1 and efc_spc_fuse_clk2 are specifically for loading information about bad rows & columns in the various arrays within the core. This information is burned into the efuse unit on the die after the RAM test, then loaded at power-up to configure the RAMs not to use these bad rows and columns. See the documentation about the reset sequence.
In the FPGA synthesis, we don't use this at all, and these signals were not even defined as clocks. I believe they are just tied low.
If you are using these signals to configure RAMs, you'll probably need to ensure that these clocks toggle only during the reset process, and probably only before the gclk is turned on.
For FPGA synthesis, there should be only one clock within the core, with no multi-cycle paths.You'll need to set +define+FPGA_SYN for this option.
I hope this helps, Sorry that the first post had to wait so long for an answer.
