OpenSPARC T1
Hi,
I have few questions regarding possibility of making OpenSPARC T1 implementation using FPGA technology.
- What is the cost of typical FPGA device itself (e.g. Xilinx Virtex-4 or Virtex-5) and cost of required additional hardware devices to perform programming of FPGA device?
- How many OS T1 cores can we implement on typical FPGA device?
- What can be typical frequency and typical power usage of such Open SPARC T1/FPGA implementation?
Greetings and thanks in advance,
Robert
[525 byte] By [
RobertP] at [2007-11-26 8:04:41]
# 1
> Hi,
>
> I have few questions regarding possibility of making
> OpenSPARC T1 implementation using FPGA technology.
>
> - What is the cost of typical FPGA device itself
> (e.g. Xilinx Virtex-4 or Virtex-5) and cost of
> required additional hardware devices to perform
> programming of FPGA device?
The cost of FPGA varies based on die size, speed grade, volume, etc.
The range varies from a few hundred dollars to multiple thousands dollars.
Get this information from your Xilinx Sales representative.
> - How many OS T1 cores can we implement on typical
> FPGA device?
One SPARC core from OpenSPARC T1 will fit into 200K LUT
Virtex-4 Xilinx FPGA XC4VLX200. See
http://fpga.sunsource.net/ for more details.
> - What can be typical frequency and typical power
> usage of such Open SPARC T1/FPGA implementation?
>
Estimated Freq. reported by Synplicity tools after synthesis
is 57Mhz, actual Freq. after Xilinx place and route will be lower than
this. But then you need to optimize to get it to higher freq.
See Xilinx datasheet for XC4VLX200 for power consumption.
> Greetings and thanks in advance,
>
> Robert
