micro-architecture documents

Hello:

Besides your IEEE MICRO paper, I'm unable to find any documentation about the Niagara's micro-architecture. More specifically, I'm looking for details such as: L2 cache bank conflict penalty, are the caches -indexed and -tagged using physical addresses, FPU exposed pipeline latency etc. Digging out this information from the RLT seems impossible. I know that Intel has such documents for the Itanium processor (called: Processor Reference Manual for Software Development and Optimization). Are there any such document for the Niagara? Thank you,

-ram

[580 byte] By [t1_model] at [2007-11-26 8:02:23]

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# 1

Check out the "UltraSPARC Architecture 2005" and"UltraSPARC T1 Processor Supplement to UltraSPARC Architecture 2005"docs which are at : http://www.sun.com/processors/documentation.htmlThey answer some of the questions you are asking.-Jeremy

jeremyweek at 2007-7-6 20:35:00 >

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# 2

Thanks, but these documents talk about the architecture. Could not find information about the micro-architecture. -ram

t1_model at 2007-7-6 20:35:00 >

# 3

Sun is working hard to release much more detailed micro-architecture information. I don't know the exact schedule, but either it was just released in the OpenSPARC T1 source code "tar-ball", or will be in a release coming soon.I'm not sure if it will be in the "tar-ball" or separately downloadable -- I will check with some others here and see if I can get them to post a more authoritative response in this thread.

= Dave

dweaver at 2007-7-6 20:35:00 >

# 4

Hi Dave:I was wondering if you have further information about the release of the micro-architecture documents. Thanks,-ram

t1_model at 2007-7-6 20:35:00 >

# 5

I'm responsible for the Architecture spec; the micro-architecture doc is coming out of another dept and I don't want to make promises for them :-) ... but rumor has it that the micro-architecture document is scheduled for release in the next month (August).

dweaver at 2007-7-6 20:35:00 >

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