I am interested in synthesizing each pipeline stage individually. From the modules in sparc.v it is not clear how these are spread across the 6 stages. Except for some that are obvious like sparc_exu, most of them are not self-explanatory.
Is there anywhere some documentation on this mapping? If not, is there any way to identify the inter-stages registers?
Any help or advice is welcomed. Thanks.
The SPARC core pipeline diagram is in Slide 7 of the following
presentation at Multi-core conference.
http://opensparc.info/cgi-bin/goto.php?w=http://opensparc.sunsource.net/conf/mu lticore/06/Niagara_Microarchitecture_ooox-Poonacha.pdf
The individual pipeline stages may be combined in to one hierarchical
block and hence will not be synthesizable separately. Here is high
level description of blocks and pipeline stages, most of the pipeline
stage logic is the 3 blocks :
1. IFU (Instruction Fetch Unit) includes following pipeline stages -
Fetch, Thread Selection and Decode.
It also includes Instruction Cache complex.
2. EXU (Execution Unit) includes the Execute stage of the pipeline.
3. LSU (Load/Store Unit) includes Memory and Writeback stages
and Data Cache complex.
In addition, TLU (Trap Logic Unit) has Traps and PC logic, SPU has Crypto
features. FFU is Floating point Front end unit. MMU has memory management
unit.
