In the file, $DV_ROOT/design/sys/iop/common/rtl/swrvr_clib.v
when I'm doing synthesis with ambit
build gates, it is unable to synthesize the following statement
when used with only asychronous reset.
q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : ((se) ? si[SIZE-1:0] : din[SIZE-1:0] );
when I replaced the code the statment by its equivalent if-else
,it is able to synthesize.
(I should technically fork this thread to another topic, anyhow ... )
For future reference, I read elsewhere on the forums that 2005.09 was required. I was able to synthesize some code with 2004.06 after making some modifications in the RTL, but obviously I don't intend to keep that up.
In that process, I ran into a number of "out of memory" errors. Blame that on the aging Sun Blade 2000 that I have access to. It is seriously lacking in physical and virtual memory (1GB/1.6GB).
Time permitting, I'd like to give it a another shot on a Core2 Quad workstation that I have here. Admittedly, DC isn't multi threaded, but that's besides the point. I'm not sure how much success I'll have getting Design Compiler up and running since the workstation runs Fedora Core 4. Suggestions, anyone?
Also, for curiosity's sake, once I have synthesized the design for the technology I have access to, how much computational power will I need to successfully perform physical design tasks such as a successful place & route, clock tree synthesis or power planning. The purpose here is to familiarize myself with an actual design while still at school. I have some experience with all of this, but the designs were trivial by comparison.
Thanks for your replies!
Edmond
Message was edited by:
edcote
