simulation error
Hi, guys
Tried to run some simulation and errors kept showing up. For example, in /design/sys/iop/ctu/rtl/ctu_clsp_pllcnt.v, line 298
always @(/*AUTOSENSE*/ `RSTSM_FREQ_CHG or `RSTSM_PLL_LCK
ncverilog keeps complaining about this. I am new to verilog, but the above statement does looks suspecious. It's weird to put a defined constant value in a always statement.
[390 byte] By [
jon_voight] at [2007-11-26 7:47:48]

# 1
It's not a good practice to use constants in the always statement, but
many simulators ignore it. The version of NCVerilog mentioned
in the Sun documents does not complain about this. You may be using
different version of the NCVerilog simulator.
Anyway, it will be fixed in the next release of the source code.
# 2
Hi Guys,
I also encountered simulation problem while using ncv version 5.4. NCV coredump on always statement or initial statement. Please help!
ncverilog: 05.40-p004: (c) Copyright 1995-2004 Cadence Design Systems, Inc.
ncsim: 05.40-p004: (c) Copyright 1995-2004 Cadence Design Systems, Inc.
=== OpenSPARC T1 PLI Version 1.0 ===
Copyright (c) 2001-2006 Sun Microsystems, Inc. All rights reserved.
Loading snapshot worklib.core1:v .................... Done
ncsim> source /tools/eda/cadence/ldv/tools/inca/files/ncsimrc
ncsim> run
ncsim: *internal* (rts_seghandler - SIGSEGV unexpected violation pc=0x498f9e8 addr=0x1d000000
Always stmt (file: /export/home/nzhang/OpenSPARCT1/design/sys/iop/ctu/rtl/ctu_clsp_clkgn_1div.v, line: 215 in worklib.ctu_clsp
_clkgn_1div [module])).
Please contact Cadence Design Systems about this problem
and provide enough information to help us reproduce it.
ncverilog: *E,SIMERR: Error during Simulation (Core Dumped), exiting.
# 3
The simulation works with NCVerilog version 5.3. The always statementin the file design/sys/iop/ctu/rtl/ctu_clsp_clkgn_1div.v does nothave any problems (like constants in the always statement).Please contact Cadence Design Systems about this problem.
# 4
Have anybody from Sun or the community compiled and run OpenSPARC regression successfully using NCVerilog version newer than 5.3 ? Thanks in advance!
# 5
The problem may not be related to particular version of the
NCVerilog, but the problem is related to which
C++ compiler is used to compile PLI code and Link PLI code.
NCVerilog binary files seems to be compiled using older Sun Compilers,
like SC4.2 or SC5.0 and if you are using SunStudio Compiler like
SunStudio Version 11, you will have problems
during NC Verilog run time and none of the tests will pass.
Try using SC4.2 or SC5.0 and then it should work or contact Cadence
to get binaries which will work SunStudio Compiler.