synthesis issues_2
Issue1: "unmapped modules .."and"instead of AND2X1"
With the current script we have ,we are able to synthesize all individual
modules, except 3 black boxes.While synthesizing the top module
i'm reading individual adb files and also some verilog modules like repeaters flop_rptrs_xa0,bw_clk_gl_vrt_all etc. andWe are using "Encounter" for the P & R. In that case , i'm getting some unmapped modules like and instead of AND2X1.
Error: Missing module definition in netlist for and
Issue 2:
I ran synthesis for the top module as in case 1 except that I read only adbs without verilog modules flop_rptrs_xa0,bw_clk_gl_vrt_all etc like repeaters etc.Then I dont have any unmapped modules, but the same netlist when read by Encounter for " P & R "
it is showing errors
ERROR: [verilog/top_wortl_netlist.v:440846]: Mismatched net number and bus pin number at ).
Number of nets (16) more than bus (outdata_vec_in) pin number (2). Ignore the rest of nets.
Please check CDUMP/LEF file or add module definition.
.how to solve this problem.
Other strategy
I cant rely on my script and at the same time , I dont
have Synopsis Design Compiler to use the scripts provided by the SUN.
So I converted the synopsis script into pks ac shell readable script.
Again the question is wheather to go for 233 blocks or my 22 modules
Because
If I synthesize all the 233 blocks , can I generate netlist for the top module
OpensparT1 by reading 233 adbs(I'm expecting memory problem)
Thanks to sun for understanding so many problems.I need ur help
to solve the problem also.
