Documents for sparc<->pcx interface
Hi,
I'd like to extract sparc core and build a SoC bus interface for the core. However, I am wondering if there is any document for the core interface.
I am asking because I noticed that there is a "Simple RISC" project that is also doing the same thing and I am wondering if they got a hold of such document. Or, did they just run a lot of simulation and study the waveform on the interface.
If there is such information, I'd like to get one too.
Regards,
[489 byte] By [
mutex2k] at [2007-11-26 6:45:48]
# 1
Hi,
The module/block level interface documents including SPARC core to PCX are
currently not available. Please run the simulations and look at the waveforms
for details. Here is some information on this SPARC to PCX interface and
pointers to get more information :
- PCX packet has 5 possible destinations - 4 L2 Banks, and 5th is
for non-cache (shared between FPU and IOB).
$DV_ROOT/design/sys/iop/sparc/lsu/rtl/lsu_qctl1.v has logic
to generate PCX requests.
- The spc_pcx_data_pa has 124 bits which includes :
64 bits of data, 40 bits of address and control signals.
File $DV_ROOT/design/sys/iop/sparc/lsu/rtl/lsu_qdp1.v has
logic to generate spc_pcx_data_pa.
- The Read data is returned on CPX interface. Which is 145 bits
bus includes 128 bits of data and control.
- See $DV_ROOT/design/sys/iop/include/iop.h for detailed
bit positions for PCX/CPX packets and packet types for PCX/CPX.
# 2
Thank you for your reply. I will look into the source code. I hope I can find out the full spec of the protocol. Will such document avaliable in the future? An open source project may not need the full implementation of T1 including the switch, J-Bus and multiple processor cache. Study the waveform and source code is always the last option and may ended up with some misunderstandings.
Regards
# 3
Hello, sorry for the late reply. You are definitively right.
Here at Simply RISC we are doing exactly what you say: we are trying to get an instance of one single SPARC Core working inside a Wishbone wrapper.
Since there are no documents available at the moment we are just looking at the waveforms -- as you can imagine it is not a trivial task!
As soon as we have the SPARC-to-Wishbone bridge working (even partially) we will publish it (under the GPL) on the SRISC.com website.
Have a nice day!
Fabrizio Fazzino
