SDC timing exceptions for OpenSparc t1

In the synthesis build scripts for the Niagra processor I can see that there are provisions for passing SDC FALSE_PATH and MULTI_CYCLE_PATH statements into the synthesis.

However I can't find any files containing any actual paths that are marked as FALSE or MULTI_CYCLE.

Can we get these for a typical implementation?

[337 byte] By [richfaris] at [2007-11-26 6:10:33]

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The scripts have templates to define FALSE_PATH and Multi-cycle-paths,

the actual timing of design depends on the Silicon process technology

and the physical design. So these paths are implementation dependent.

The design is mostly synchronous and pipe-lined and

there is no generic list of the multi-cycle/false paths for a

typical implementation.

OpenSparc at 2007-7-6 13:44:01 >

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SDC timing exceptions for OpenSparc t1

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