FPGA implementation of the OpenSPARC T1
Hi,
I am interested in mapping the RTL of the OpenSPARC T1 onto an Altera FPGA preferably using Altera's CAD tool (Quartus II). I want to do this for just one SPARC core and figure out what area/delay/power numbers I end up with.
1. Could anyone here give me tips on how to go about this task so that I can have an efficient implementation?
2. Does anybody have a feel for what kind of performance is obtainable from an FPGA? The actual UltraSPARCs seem to run at 1.2 GHz; what can an FPGA potentially achieve?
Thanks a lot,
Shyam
# 1
Hi,
I think that this is a very interesting project, and maybe some people should coordinate on it. I look at the openSparc code but I did not try to synthesize on FPGAs. This is my guess:
-You should be able to fit just one core in a medium size FPGA (EP2S60). I do not think that you'll go over 25MHz without retunning the design for FPGA.
-Two big area consumers that need to be addressed are the Register file and the mul32.
The register file has 3 wr and 2 rd ports with sliding window. This type of configuration can not use memory banks (at most 1 write port). Something needs to be done to reduce space (less windows?, remove 1 write port would be the best)
The mul32 uses a booth encoder. This is very neat for ASIC, but useless overhead for FPGAs. Just encode the multiplication (* in verilog) to use the built-in multiply units.
I am sure that more things need to be addressed even before you start to run on the FPGA (the previous issues are just to synthesize for FPGA)
# 2
Thanks. Interesting comments. I was also thinking that a direct implementation of the existing Verilog would probably end up being relatively inefficient, and that certain implementation decisions would probably have to be different for an FPGA.
At another forum where a similar topic was being discussed somebody mentioned that the OpenSPARC Verilog that has been provided is a structural netlist with excessive hierarchy and without flip-flop inference. It was suggested that such Verilog could lead to inefficient synthesis. Am not sure how well a synthesis tool can remap this Verilog to a target FPGA architecture.
In any case I guess the first step is simply to try and synthesize this for an FPGA and see what one ends up with. Then one can get a sense of where the inefficiencies are and how to overcome them.
Currently I am hampered because our Synopsys DC environment is not appropriately set up. I tried compiling using Altera's Quartus II but got too many errors.
I think your suggestion of some people coordinating on this activity is a very good one. We can do a divide and conquer.
Thanks,
Shyam
# 3
Check out the Synplicity FPGA synthesis software.www.synplicity.comCheckout their Support and Partners program for University research..
# 4
The Verilog code is good for tools like synplicity. The code does not use always @(posedge clk), but it has a flop library for that functionality. I tried and Synplicity Pro has no problem with that.
No need to recode to give a quick try. May require some rework to do an efficient mapping.
# 5
Tar file version 1.1 released today enables
FPGA implementation of the SPARC core,
Floating Point Unit (FPU) and Cross bar.
The Synplicity scripts to map the RTL to Altera or Xilinx
FPGAs are included with FPGA version of the SRAM models.
Please download version 1.1 from the http://www.opensparc.net website.
Also, see OpenSPARC FPGA project website http://fpga.sunsource.net/
