Chipipedia CP1

Yes, superscalar is a microarchitectural feature that can/should be included.

I think a superscalar implementation can indeed issue multiple operations simultaneously, but it does not have to execute and/or commit them in one cycle (or any particular amount of time).Consider the common example of a processor that issues an integer operation and a floating-point operation simultaneously .... chances are the float op takes more than one cycle to execute, and certainly won't commit in one cycle, whereas the integer op is likely to complete much faster (the total latency may still be several cycles, depending on the pipeline).

So I might suggest an amendment, something like:

SUPERSCALAR:a microarchitectural implementation technique that allows two or more instructions to issue simultaneously.

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Granted, "issue" then requires definition; the definition in UltraSPARC Architecture 2005 is:

ISSUED:

(1) A memory transaction (load, store, or atomic load-store) is said to be "issued" when a virtual processor has sent the transaction to the memory subsystem and the completion of the request is out of the virtual processor's control.Synonym for initiated.

(2) An instruction (or sequence of instructions) is said to be issued when released from the virtual processor's instruction fetch unit. Typically, instructions are issued to a reservation station or other buffer of instructions waiting to be executed. (Other conventions for this term exist, but this specification attempts to use "issued" consistently as defined here.) See also dispatched.

dweaver at 2007-7-6 13:34:37 >