I have been trying to run regression tests (for core1) with modelsim as I don't have access to other simulators. After all the environmental variables are set it comes down to the sims command, after a lot of trial and error the best command I could find is sims -sim_type=mti -group=core1_mini ...

Hi all,few days ago we have released the S1 Core and then we havecreated a project page for it at: http://s1.sunsource.net/You can read the full press release of the shipment onseveral sites, for instance on http://s1.sunsource.net/servlets/NewsItemView?newsItemID=229Basically the S1 Core is a ...

We are looking for feedback from users of GCC for SPARC Systems. What is good? What is bad? What could use improvement? What kind of programs do you build with GCCFSS? Did it go easily?

Hi all!In linux ,there is a dir named "\drivers\sbus".In "Fast Ethernet, Parallel Port, SCSI" document, signales of FEPS are named "SBus Interface Signals" .First I took sbus as J-Bus.But after comparing the "SBus Interface Signals" of FEPS with J-Bus,I found they are total different.I am ...

Need some help regarding how the T1 irf works.From bw_r_irf.v, during a SWAP operation, apparently during 1 cycle, 8 registers need to move from the "active_window" reg to "globals" reg. If I understand correctly, "active_window" is made up of rf cells, and "globals" is made up of sram cells. ...

hello, allIn tag of TLB, from the CHAPTER 13 of "OpenSPARC?T1 Processor Megacell Specification", the supported virtual address width is 35-bit. But in "UltraSPARC T1?Supplement to the UltraSPARC Architecture 2005" , the supported width of VA is 48. I don't know which is right. In tag of TLB, ...

Is there anywhere I can read more about the S1 specification? Like how many physical pins were used on the package. From the rtl, S1 should have 270 signal pins. Adding on power and other misc test pins, this will make S1 have around 500 pins. Will this be a rather expensive package for a ...

Hi all,I am a newbie to the OpenSPARC project and I would like to try it out. I follow the setup instructions in the README file. I found that it requires CC compiler binaries; however, I don't have CC installed on my system. I do have gcc, g++ and cc (small letters) installed.Because of that, ...

Hi,I am struggling with the compilation under a SPARC solaris platform.Successfull Installation of packages:- SUNW0scgfss- gccWhile executing "make", I get the following error message:gcc -Wmissing-prototypes -Wformat -Dstrcasecmp=fix_strcasecmp-Dstrncasecmp=fix_strncasecmp -g -O -I. -DSUNOS5 ...

fstream.cpp:1177: internal compiler error: Segmentation FaultPlatform:Solaris 10 3/05 for SPARCSGCC version 4.0.3PATH is /opt/gcc/bin:/usr/sbin:/usr/bin:/usr/sfw/bin:/usr/css/binSource Code STLport-4.6.2 (www.stlport.org/download.html)How to re create:After installation, modify the gcc-sun.make ...

Hi!I'm trying to run a cooltst on > uname -srvmiSunOS 5.8 Generic_117350-08 sun4u SUNW,Sun-Fire-V240> cat /etc/release Solaris 8 HW 7/03 s28s_hw3wos_05a SPARCCopyright 2003 Sun Microsystems, Inc. All Rights Reserved.Assembled 12 June 2003and have the following output:cooltst.ksh v2.3.2 ...

I would like to better understand the difference between a processor and a core. If someone could point me to a document describing the differences I would appreciate it. I am specifically interested in comparing the T1 processor to other Sun processors. I also have a specific question. A T1 ...

hi all,I have a E4900 with ultrasparc 4+@1.5ghz processors which is dualcore according to sun. But in the lom or in os its showing only 4 processors. If it is a dualcore it should be 8..I think..considering other platforms. or sparc dualcore processors show only a single processor for a dual ...

Hi,we are interested in understanding the logic that generates the Packet ID that is returned to the SPARC Core through the CPX packet. At the beginning we supposed that the Packet ID in the CPX return packet was equal to the Packet ID of the corresponding PCX request packet, but this ...

hi guys:currently,I try to use the S1 module map to FPGA.When I study the bw_r_dcd(dcache Vlog module ),I find the synthesis tool will compile different module when `define FPGA_SYN or `define DEFINE_0IN.My question is the two instance are difference in function?In other word,can I use `define ...

I have a SPARCbook 6500 and was wondering were the nvram chip is on the board? if anyone can help.

HiMy sun machine doesn't have Sun Studio. In this case, how can I set the variable SUN_STUDIO?What else do I need to run SAM in my machine without Sun Studio?

How about providing LDAP support in apache for Cool Stack?

All T1 documents indicate that irf (integer register file) has 3 reading ports. But when reading through its rtl model bw_r_irf.v, I have to raise the doubt that it actually has 4 reading ports physically, which are r1, r2, r3 and r3h. Even though the addresses of r3 and r3h are very close, ...

hi allI am an newbie on OpenSPARC. I can't find the following specification: OpenSPARC T1 Processor Megacell Specification OpenSPARC T1 Processor Datasheet OpenSPARC T1 Processor External Interface These specifications above is mentioned in the OpenSPARC T1 Microarchitecture specification. ...

I am new to Sparc and also new to Shade. I am not aware of the uses of Shade. I have Shade installed on my 64 bit sparc machine. I want to run a few instructions and get myself acquainted with the software. Please let me know how to run the commands.For example I want to run the command ...

A question came up recently about the availability of a cycle-accurate simulator for OpenSPARC T1.It may not have been well -publicized, but the SESC simulator from community member UC Santa Cruz does provide cycle-accurate simulation. See ...

Hi:Has anybody succeeded in Placing and Routing work for T1? If so, could you kindly let us know what's the work flow and on what platform?Thanks!W.Wang

I am from Sun MDE Team. I met a java code that runs a little slow. I made a simple investigation to find the root cause. However I find the SPOT tool will generate a report that is quite different than the output of cpustat, cputrack. during the investigation, especially the DC_miss counter and ...

In the T1 RTL code, there are FPGA version and regular version in many blocks. My question is, are these versions functionally identical? Do they have the same timing? If I want to implement T1 core by selecting regular versions of the RTL code in some blocks and FPGA versions of the RTL code ...

I just downloaded and installed the coolstack for x64 and the install wiped out my entire /usr/local directory! Everything else that was in there is now gone: tomcat, ant, postgres... This is the pkg file: CSQamp_x86.pkgThese are the commands I ran to install: bunzip2 CSQamp_x86.pkg.bz2 pkgadd ...

Is the cool tune service suppose to keep the ndd settings after reboot? It does not appear to be..... or should I just script it?

We've just released a patch for GCCfss 4.0.3. It's located at the same place place on SDLC website (the link is on the front page (or http://www.sun.com/download/products.xml?id=44e24b9d)).Please download it, remove old 4.0.3 packages and install new 4.0.3 packages.This patch contains several ...

Hi, I have Sparc V9 machine and I have installed the Shade tool on it. I have written simple C programs like matrix multiplication to analyze using Shade.For example, I use the ifreq command and it gives me the list and frequency of the instructions executed.I am trying to calculate the CPI = ...

While OpenSPARC processor design is open, are we able to build entire SPARC hardware (whole workstation) using FPGA?

Hi,Can anyone point me to any more publications about the Niagara 2architecture. In particular I am interested in understanding the Fetchand Pick Stages. The presentations by Robert Golla and Greg Grohoskimention some aspects of the design, but I have a few unanswered questions.In particular ...

Hi,I'd like to see someone make SMF (Service Management Facility) support for Tomcat *official*. I've seen several people make their own versions. It would be nice for it to be a part of an optimised package like yours.In particular, I'd like to see manifests that set instance-specific ...

Hi,Can someone please help me understand what the "core to workload functionality" mentioned in the process analysis section, really means..++++++++++++The process analysis identifies processes/LWPs that might cause a singlethreaded bottleneck. The relationship of any process/LWP consuming more ...

Can anyone suggest me how to implement a "64:5 Multiplexer using 6 select lines"?I mean selecting only five signals from the incoming 64 signals.Can anyone suggest a Verilog RTL Implementation for it?

Can anyone let me know which PHP compile options were used when creating the CoolStack AMP? Specifically, I am looking for GD support which does not seem to be compiled in. http://www.boutell.com/gd/

Hi,I am trying to use the Spot tool and I get the following error when I use it. When I use the command:> cc -g -O -xbinopt=prepare -o qsort3 qsort3.cI get the following warning, but dosent report any errors:cc: Warning: illegal option -xbinopt=prepareWhen I use this command> spot -X ...

Does this work for Solaris 9?

The startup script included with the 64-bit version of MySQL lists paths to the 32 bit version and the $basedir variable is not set to point to /usr/local/mysql.Is this correct? # Set some defaultspid_file=server_pid_file=use_mysqld_safe=1user=mysqlif test -z "$basedir"then ...

Someone can tell me whether the default compiler option for gcc under Solaris 10 is for 32 bits or 64 bits binaries?

Blastwave perl:root:=> /opt/csw/bin/perl -V | grep archnameosname=solaris, osvers=2.8, archname=sun4-solaris-thread-multiBuiltin Solaris 10 U2 perl:root:=> /bin/perl -V | grep archnameosname=solaris, osvers=2.10, archname=sun4-solaris-64intCoolthread perl from CSQperlroot:=> ...

I'm running some tests on a T1000 with Solaris Nevada b53. I tried to install Cooltuner, but it won't install on a Nevada system. Is there a Nevada version available?Perhaps the tuning tweaks from Cooltuner have been applied to Solaris Nevada already?My application is a Solaris build server; ...

From the documentation on Porting, it says that GCC for SPARC was compiled to use the Solaris linker. Is there a way to reset GCC so it will use the GNU ld?Am running:- Solaris 10 6/06 with up to date patches on a SF T2000- have GNU ld installed in /opt/binutils/- GCC For SPARC Systems ...

Hi,I downloaded this CoolStack and was really impressed. This will definitively help new administrators in the Solaris community. I am really thankful all of the hard work.I have a question: I'm trying to install SugarCRM but it complains that PHP does not contain support for CURL, MBSTRINGS, ...

The i386 page address system has three levels: dir, page, offset. The 32 bits virtual address consists of dir, page, offset. When the process releases a virtual address to read a memory content, the MMU of i386 will translate the virtual address to physical address as follows:1,Based on the ...

I'm wanting to update my development server to php5 mysql5 and apache2. To be perfectly honest, I'm not a Solaris admin. I have Linux experience but very little Solaris experience. From reading the CoolThreads pages I honestly can't tell if these Cool Stack packages will work with OS ...

Hello All-Pardon me if this has been hashed out before. I'm seriously considering the use of some of the Cool Stack packages to run a SAMP setup. However, what I can't find anywhere is how security updates and such are managed... for example if a security bug in PHP is discovered, who's ...

hi,I downloaded the opensparc. I found only the synthesis scripts for synopsy and synplicity.Where can i find the synthesis scripts for magma? please provide the scripts if availableregards,suba

Hi!System Requirements for SAM (SPARC Architectural Model) consist aSPARC CPU based system with Solaris 9 or Solaris 10 Operating System.Can be eat an opportunity to start SAM on x86 if no how can i buy an SPARC CPU processor?

Hi all,i am very interested in OpenSPARC and multi-core cpu, but now i have only learned the archecture of simple 8 bit risc mcu and basic acknowledge about pip-line. i want to know what is the difference between 8 bits mcu and 64 bits cpu, and how the mult-core cpu works with so many cores?at ...