I have seen requests for Open Boot PROM (OBP) source code forOpenSPARC T1. The OBP binary is already published for OpenSPARC T1with SAM and Legion simulators.If the OBP source is made available, what is the potential use ofthis source code: Is it needed for reference only orfor use with ...

Hi, I have been playing with bit tools (binopt), and it is very interesting platform that may be used to evaluate multiple alternatives. Is it possible to create "new" optiization passes? E.g: imagine that I want to replaceall the shifts for multiplications (pretty useles). How can I write a ...

Hi,I'd like to extract sparc core and build a SoC bus interface for the core. However, I am wondering if there is any document for the core interface.I am asking because I noticed that there is a "Simple RISC" project that is also doing the same thing and I am wondering if they got a hold of ...

I'm using pks for generating netlist.I dont have a clear strategey for synthesizing Opensparc.I'm working in two ways.1.I divided Opensparc into 18 modules ,e.g. fpu, iobdg etc.I 'm synthesizing each one.then generating top level netlist reading individual modules.I got some primitive cells ...

1.I've generated SRAMS from artisan compiler .but they are generated without scan inputs whereas the RAMS present in Opensparc have scan i/p s.So when I'm adding RAM lib files , synthesis tool is showing error that scan i/ps are not found.can I synthesize srams with scan i/p and o/p.do i have ...

Issue1: "unmapped modules .."and"instead of AND2X1" With the current script we have ,we are able to synthesize all individual modules, except 3 black boxes.While synthesizing the top modulei'm reading individual adb files and also some verilog modules like repeaters ...

To solve RAM problem faced with scan pins which are not present in the artisan compiler o/p , I tried to put a wrapper to separate scan pins.But the rtls have some other extra pins not present in compiler o/p.For example reset pin , i.e rst_l.So mapping these pins to the pins present in the RAM ...

Hi,I would like to run simulations using Legion. However, I have not found any information of how can I launch simulations and how can I get performance results.How could I launch simulations with Legion? Where can I find manuals related to Legion ...

Hi thereIs there any plan to open-source the T2 core? I have read that each core has a dedicated FPU and apparently it is now complete?

What's going wrong?=> Running cpustat... (05/26/06 14:57:05)=> Runtime (cpustat) ended... (05/26/06 14:57:50)=> Running procls.sh... (05/26/06 14:57:50)=> Completed data collection... (05/26/06 14:57:50)=> Analysis of collected data... (05/26/06 14:57:50) PROCESSES FOR ...

I almost completed synthesizing all the blocks exept SRAMS.Memory compiler generatd RAM has following portsoutput [127:0]QA;inputCLKA;inputCENA;input [3:0] AA;inputCLKB;inputCENB;input [3:0] AB;input [127:0]DB;input [2:0] EMAAwhereas OpensparcT1 rtl has the followig portsinput [127:0] din; // ...

Hi,I played aroud a bit with the cooltst tool on a V210 (sparc)SunOS hostname 5.9 Generic_117171-12 sun4u sparc SUNW,Sun-Fire-V210When examening the logfiles I noticed a lot of "/usr/sbin/cpustat: not found" lines in /tmp/000/hostname/NM_cpustat_outThis message is not displayed on stdout of ...

Can sun help me out about all the clock domaims presentin OpensparcIt would be of great help for me to time constrain all the paths properlyI need the clock info. if the following modules are considered as top timing moduleOpensparcT1 ...

Hi, guysTried to run some simulation and errors kept showing up. For example, in /design/sys/iop/ctu/rtl/ctu_clsp_pllcnt.v, line 298always @(/*AUTOSENSE*/ `RSTSM_FREQ_CHG or `RSTSM_PLL_LCKncverilog keeps complaining about this. I am new to verilog, but the above statement does looks suspecious. ...

In the file, $DV_ROOT/design/sys/iop/common/rtl/swrvr_clib.vwhen I'm doing synthesis with ambit build gates, it is unable to synthesize the following statement when used with only asychronous reset. q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : ((se) ? si[SIZE-1:0] : din[SIZE-1:0] );when I replaced ...

I am interested in synthesizing each pipeline stage individually. From the modules in sparc.v it is not clear how these are spread across the 6 stages. Except for some that are obvious like sparc_exu, most of them are not self-explanatory. Is there anywhere some documentation on this mapping? ...

Hello:Besides your IEEE MICRO paper, I'm unable to find any documentation about the Niagara's micro-architecture. More specifically, I'm looking for details such as: L2 cache bank conflict penalty, are the caches -indexed and -tagged using physical addresses, FPU exposed pipeline latency ...

Hi,I have few questions regarding possibility of making OpenSPARC T1 implementation using FPGA technology.- What is the cost of typical FPGA device itself (e.g. Xilinx Virtex-4 or Virtex-5) and cost of required additional hardware devices to perform programming of FPGA device?- How many OS T1 ...

Hello, under advisement, I've switched the new SUNW0sgcc 4.0.2 downloadedfrom cooltools.I've come across a few minor issues compiling some packages,but nothing major.Until I got to GNU aspell.Now it is giving me nothing but grief. I am passing the following configure options to ...

i tried to install vlc0.8.5 on my Ultr80when i am running the script to build the binary i get the folowing error:gcc (GCC) 4.0.2 (gccfss)Copyright (C) 2005 Free Software Foundation, Inc.This is free software; see the source for copying conditions. There is NOwarranty; not even for ...

I want to study computer architecture by reading opensparc source code . but the source has no any comments, no description about each modules, files.because I am one newbie, i don't understand the module name, such as "module bw_clk_gl" , what is the meaning"bw"? what is the meaning "gl"?are ...

Hi, Before telling you my dilemma I must say that english is not my native language and my question in not directly related to OpenSPARC.About a year ago I found an opensource multiprocessor project called Leon3 from Gaisler Research. It's based on SPARC V8 definition, fully compliant, and ...

I'm working on timing closure of one sparc core.It seems there are so many multicycle paths.Any document available whcih has the list of multicycle/false paths.to one sparc core, three clock i/ps are present.1.gclk > 1200 Mhz2.efc_spc_fuse_clk1 > 240 Mhz3.efc_spc_fuse_clk2 > 240 ...

I see that these files are simlinked to v8/libm* (the same inline lib), this means that it always links v8 code. I've try to pass -xargs=v8plusb when linking and linker used lib/libmvec.a (which is v8/libmvec.a). Does it mean, that I have to relink symlinks of these files to corresponding ...

I am looking for licensing information regarding AU audio format. I have fill up the on line Contact Form but still couldn't get to the appropriate contact person to response to my enquiry. I am looking for licensing information on behalf of my company, we have new internet radio project where ...

Anyone else move an Oracle instance to a coolthreads system? We have and are having a perceived performance problem. Users complain of slowness but the system doesn't show anything.

When compiling various packages using the SUNW0gcc, I am seeing a lot of these warnings:warning: pointer targets in initialization differ in signednessThis happens when compiling OpenSSL 0.98 against PHP-5.1.4. Should I be concerned, or is gcc smart enough to figure it ...

hello,T1 supports TSO memory model. TSO allows the later loads bypassing earlier stores. But T1 is a single-issued processor, the later loads can't bypass the earlier stores. I think T1 is a nature Sequential Consistency processor other than a TSO processor.Thanks.

Hello,we've been working on a joint project for telco bearer plane applications on CMT.We started the project using gcc for Sparc and we switched to Sun Studio compiler when we hit some bugs in gcc (optimized mode was not completely stable). The switch took a few weeks due to syntax ...

hi,I use Synplify pro to synthesis the sparc module.It gives me some error informations.how could them occur?what can I do?@E: CL172 :"E:\sparcsyn\bw_r_rf32x152b.v":64:16:64:25|Only one always block may assign a given variable local_dout[151:0]@E: CL172 ...

Hehe, I have a dream .One day ,downloads the sof file of opensparc system into an FPGA board, downloads the zImage of Linux into the memory of the FPGA board,then it tells:Hello ,Opensparc&Linux.......In the past 1year, I tried to understand the kernel of Linux.And now, i am interested in ...

I have HTTP parser written in C, which is a single file, about 15000 lines of C code. I also have a test program that calls HTTP parsing function in a loop for a range of HTTP headersCompile executable with SunPro compiler:# /opt/SUNWspro/bin/cc -o proftest.sunpro -xO3 -xtarget=native ...

Hi all,I am trying to compile Samba 3.0.23a with AD support. I have successfully compiled OpenLDAP 2.3.24, MIT Kerberos 5 Release 1.5 and openSSL 0.9.8b. While making samba, I get the output as in the code section.I have configured the Samba build with the following options../configure ...

Can't locate strict.pm in @INC (@INC ...

Hi all,we are ready to release the Wishbone bridge for the SPARC Core but we need answers for some questions that we could not solve by ourselves. The answers to these questions should be trivial for you but they are very important for us.1) CPU_ID and Mask_IDFor core1_mini simulations we have ...

When compiling a particular piece of c++ code with SUN GCC for sparc system version 4.0.2, i get the following assert from CG :cg: assertion failed in file ../src/common/POINTERSETQUEUE.cc at line 225cg: CG_POINTERSETQUEUE.search: non-unique funccg: 1 errors

Hi, Would you like to help me on how to resolve a problem appear when I have reboot a station SS20. On rebooting, this message is written:===============Copyright (c) 1983-1996, sun microsystems, inc.Fatal System fault : sirp = 40000000Async fault from module 0 : afsrb301000 ofar = ...

I have now finished running the cooltst.ksh script on my large simulation. Now, I am getting a Yellow result with a % of around 1.1 to 1.2% . How do I interpret this? If I will only have 1 process in use at a time, is it likely to matter if I get a borderline value?Many thanks for your ...

Hi,will Logical Domains with Solaris 10 support Dynamic Reconfiguration?- is it possible to change the number of assigned virtual processors dynamically without reboot of the LDOM?- is it possible to add/remove RAM to/from a LDOM witout reboot?- will dynamic reduction of RAM be restricted by ...

Hi,what is the management interface for Logical Domains, which is used to create/modify/delete LDOMs, assign (CPU-/RAM-/IO-) resources to LDOMs, start/stop/reset LDOMs, backup/restore LDOM configuration,..?Will this management be performend from within a LDOM? Any LDOM? Or is there the concept ...

Hello,I am running the core1 regressions with the sims script.Now I would like to rerun a single diag/testcase from the regression.Looking into the core1.diaglist it does not appear to be easy to extract the right information by hand. So ideally I would like to list all diags in the core1 ...

1,How to test opensparc T1 ?DVGuide tells System Requirements are SPARC?systemsrunning the Solaris 9 or Solaris 10 Operating System.I have no SPARC System and I am a stranger to Solaris.My computer is installed Windows XP and Fedora Core 5 Linux. It drives me crazy...But I have to go on with ...

I need some help since I think the FP usage I am seeing is artificial.I am running cooltst on a v880 server running Solaris 8 with 4 900mh IIIi processors. I am seeing 1.2 - 1.8 FP usage over the course of the day (we ran cooltst hourly). I saw another discussion where it mentioned some of the ...

According to the man page"-MD is equivalent to -M -MF file, except that -E is not implied. The driver determines file based on whether an -o option is given. If it is, the driver uses its argument but with a suffix of .d ..."However,g++ -MD -c foo.cpp -o foo.oproduces foo.d.d instead of ...

http://www.hotchips.org/hc18/program/conference_day_two.htm#session9"Niagara2: A Highly-Threaded Server-on-A-Chip" by Greg GrohoskiIt'd be great to see the presentation slides/paper available as a download.There's not many write-ups of the talk, but here's ...

Hi ,all.Sun provides a Source Browser in http://opensparc-t1.sunsource.net/nonav/source/verilog/html/verilog.html.It is so convenient and easy to use. But our web server is unstable.Occasionally My computer will be cut off connection from the Internet.My question comes: Is there any desktop ...

HiAfter setting up SAM_ROOT and SUN_STUDIO, I ran run_sam.sh.But SAM is stuck only showing "Connecting to compute:33269 netcons: control-character is ^]".I waited 10m. In general prompt, not "Guest Console", the following message is shown without change in "Guest Consol",-loading python ...

Hi all,In OpenSPARC micro-spec 3.4.3 "PCX Arbiter Control Flow", Sun proposed a round-robin scheme (toggle priority direction every cycle). [1] One clock is left-to-right (C0-C7), another clock is right-to-left(C7-C0). So C3 and C4 have the lowest priority, is it right?[2] Is it a method that ...

Hi,I just downloaded the latest release with the x86 linux binaries. Trying to run regression with VCS and got some linking errors with the PLI libraries. I went into the lib directory and couldn't find these symbols in the .a files. However these symbols seem to exist in the SunOS libs. Has ...